Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-11-21
1999-11-30
Brown, Peter Toby
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438622, 438627, 438642, H01L 2170
Patent
active
059942118
ABSTRACT:
Provided is a method and composition for RF sputter cleaning of contact and via holes which provides substantially uniform charge distribution in the holes and minimizes electron shadowing. This is accomplished by isotropically depositing, such as by PVD, a layer of conductive material at the wafer surface surrounding a hole and down the sides of the hole. Isotropic deposition is such that in high aspect ratio trenches and holes deposition is heaviest at the top and minimal at the bottom (due to the deposition shadowing effect). The deposited conductive material is preferably a metal that is also used as a liner in the holes prior to depositing the plug material. The conductive material provides path for negative charge otherwise accumulating at the top of a hole during RF sputter cleaning to reach the bottom of the hole and thereby prevents accumulations of charge of one polarity in and around the hole. Thus, the stress on the gate oxide caused by conventional RF sputtering, described above, is relieved.
REFERENCES:
patent: 3816185 (1974-06-01), Toledo et al.
patent: 3868217 (1975-02-01), Hollingshad
patent: 4076575 (1978-02-01), Chang
patent: 4343660 (1982-08-01), Martin
patent: 4497713 (1985-02-01), Geiger
patent: 4544445 (1985-10-01), Jeuch et al.
patent: 4624864 (1986-11-01), Hartmann
patent: 4649025 (1987-03-01), Hwa et al.
patent: 4663053 (1987-05-01), Geiger
patent: 5017029 (1991-05-01), Andou et al.
patent: 5266516 (1993-11-01), Ho
patent: 5533635 (1996-07-01), Man
patent: 5712194 (1998-01-01), Kanazawa
patent: 5714418 (1998-02-01), Bai et al.
Presentation slides at CMPUG Annual Symposium, entitled "Alumina-SiO.sub.2 Interactions Under Conditions Relevant to Post-CMP Cleaning of W-Slurries", by I.J. Malik, R. Emami, C. Raghunath, and S. Raghavan of OnTrak Systems, Inc., Milpitas, California, Dec. 1996.
Catabay Wilbur
Hsia Wei-Jen
Wang Zhihai
Brown Peter Toby
Guerrero Maria
LSI Logic Corporation
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