Method and circuitry for programming floating-gate memory cell u

Details Method and circuitry for programming floating-gate memory cell u Method and circuitry for programming floating-gate memory cell u

1994-05-06

1995-05-02

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

365185, 365900, 257289, G11C 700

Patent

active

054126037

ABSTRACT:
The drain-to-source voltage and current for programming a selected nonvolatile memory cell 10 are achieved efficiently by pumping the source 11 of a selected cell 11 to a voltage less than the voltage VSS at the reference-voltage terminal of the memory cell array while, at the same time, pumping the drain 12 of the selected cell 10 to a voltage greater than the voltage VCC, which may be 3 V, at the supply-voltage terminal of the memory cell array. The cell substrate W2 is pumped to a voltage close to the voltage of the source 11 and, optionally, below the voltage of the source 11. One or more simple charge-pump circuits convert the output of the voltage supply VCC to a source-drain voltage and current capable of programming the selected nonvolatile cell 10 by hot carrier injection.

REFERENCES:
patent: 4016588 (1977-04-01), Ohya et al.
patent: 4601020 (1986-07-01), Arakawa et al.
patent: 4687312 (1987-05-01), Doung et al.
patent: 5267209 (1993-11-01), Yoshida
patent: 5313429 (1994-05-01), Chevallier et al.
patent: 5341342 (1994-08-01), Brahmbhatt

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