Method and circuitry for modifying data words in a multi-level d

Details Method and circuitry for modifying data words in a multi-level d Method and circuitry for modifying data words in a multi-level d

1996-01-25

1998-09-22

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711145, 711144, 711141, 711122, G06F 1300, G06F 1200

Patent

active

058130349

ABSTRACT:
A multi-level distributed data processing system includes: 1) a system bus having a main memory coupled thereto; 2) multiple high level cache memories, each of which has a first port coupled to the system bus and a second port coupled to a respective processor bus; and, 3) each processor bus is coupled to multiple digital computers through respective low level cache memories. Further, each low level cache memory stores data words with respective tag bits which identify each data word as being shared, modified or invalid but never exclusive; and, each high level cache memory stores data words with respective tag bits which identify each data word as being shared, modified, invalid, or exclusive. By identifying a data word in a low level cache memory as shared, even when that data word is not in any other low level cache memory, the high level cache memories are able to prevent two computers on separate processor busses from modifying that data word differently; and in addition, the high level cache memories are able to track the data words which get modified.

REFERENCES:
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patent: 5241641 (1993-08-01), Iwasa et al.
patent: 5394555 (1995-02-01), Hunter et al.
patent: 5551005 (1996-08-01), Sarangdhar et al.
patent: 5581729 (1996-12-01), Nishtala et al.
patent: 5623628 (1997-04-01), Brayton et al.

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