Method and circuitry for erasing a nonvolatile semiconductor mem

Details Method and circuitry for erasing a nonvolatile semiconductor mem Method and circuitry for erasing a nonvolatile semiconductor mem

1992-04-21

1994-07-05

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Erase

365184, 365200, 365201, 365210, G11C 700, G11C 702

Patent

active

053273834

ABSTRACT:
Circuitry for independently controlling the erasure of a flash memory including redundant rows for replacing shorted rows within the memory array is described. An erase command fires a sequencer circuit, which schedules the controllers that execute the tasks of an erase event. By nesting the control of erase events, the sequencer circuit allows easy modification of erase events. The sequencer circuit fires a precondition controller upon receipt of an erase command. The precondition controller then manages the preconditioning of the memory array, including memory cells within shorted rows. The precondition controller does so by disabling the replacement of shorted rows with redundant rows. During preconditioning each memory cell is programmed to a logic 0, before the memory cell is erased to a logic 1, to prevent the overerasure of memory cells during subsequent erasure. Afterward, the sequencer fires the erase controller. The erase control circuit then manages erasure. The circuitry also includes a postcondition controller and a program controller.

REFERENCES:
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patent: 5097446 (1992-03-01), Shoji et al.
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patent: 5134583 (1992-07-01), Matsuo et al.
patent: 5214605 (1993-05-01), Lim et al.
patent: 5222046 (1993-06-01), Kreifels et al.
patent: 5237535 (1993-08-01), Mielke et al.

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