Method and circuitry for debugging/updating ROM

Details Method and circuitry for debugging/updating ROM Method and circuitry for debugging/updating ROM

2004-10-25

2008-11-18

Le, Dieu-Minh (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C711S102000

Reexamination Certificate

active

07454663

ABSTRACT:
A read only memory circuit for debugging and updating, the circuit includes read only memory, debug program memory, program counter, and compare and load unit. In the circuit, the compare and load unit detects instruction-read-memory-address from the program counter. If the instruction-read-memory-address is a predetermined main program address, the compare and load unit serves to transmit a debug address in the debug program memory to the program counter to update the original instruction-read-memory-address for debugging.

REFERENCES:
patent: 3588835 (1971-06-01), Ensbelt
patent: 5592613 (1997-01-01), Miyazawa et al.
patent: 5953530 (1999-09-01), Rishi et al.
patent: 6915416 (2005-07-01), Deng et al.
patent: 2001/0052114 (2001-12-01), Koh et al.
patent: 2002/0174385 (2002-11-01), Cofler et al.
patent: 2001-265620 (2001-09-01), None
patent: 2002-007156 (2002-01-01), None

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