Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-06-11
2003-02-11
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S106000
Reexamination Certificate
active
06518792
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electronic systems, and more particularly, high-speed digital signaling.
2. Description of the Related Art
Operating speeds of digital systems have increased significantly in recent years. System that can transmit data from a drivers to receivers at data rates of 1 GB/s are becoming commonplace. In order to ensure that transmitted data is properly recovered by a receiver circuit, certain conditions must be met.
Eye patterns are well known in the art of digital signaling. Parameters that define an eye pattern include both setup time and hold time. Eye patterns are often times used to characterize various types of digital I/O links, such as source synchronous lines and links. Source synchronous I/O includes the transmission of a clock signal at the source along with the transmitted data signals. In order for a source synchronous receiver to properly recover transmitted data, the eye pattern must allow for sufficient setup time and hold time with respect to the forwarded clock.
Source synchronous data lines, as well as many other types of high-speed digital signaling links, typically include what are known as center-taped terminated (CTT) I/O buffers.
FIG. 1
shows an exemplary CTT I/O buffer. CTT I/O buffer
10
includes a driver circuit
12
and a receiver circuit
19
coupled by transmission line
14
. Transmission line
14
is referred to as center-taped terminated due to the presence of pull-up resistor
16
and pull-down resistor
18
. These two resistors may be of equal resistance value. The resistance value of these resistors may be chosen to effectively terminate the transmission line, thereby preventing or minimizing reflections and other transmission line effects. However, despite effective termination of the transmission line, factors causing signal degradation may still exist.
Frequency dependent dispersion is one factor that may affect a signal transmitted on a transmission line. Frequency dependent dispersion may result from such factors as skin effect and dielectric loss resulting from the transmission line medium. Frequency dependent dispersion may result in signal edge degradation and amplitude attenuation. These effects may become more acute at GB/s signaling speeds, in part due to the high data rate. Further compounding the problem may be the high frequency content of the signal edges on low-to-high and/or high-to-low transitions.
Frequency dependent dispersion may result in what is known as data dependent jitter. Data dependent jitter may be observed as a frequency dependent timing delay vs. data patterns associated with various frequency components. Data dependent jitter may distort the eye pattern and thereby decrease the valid setup and hold window. Thus, the allowable setup and hold time for transmitted digital signals may be significantly reduced. This may significantly reduce the reliability of high-speed digital signaling operations.
One technique that has been developed to combat frequency dependent dispersion and its resulting data dependent jitter is known as pre-emphasis. Pre-emphasis involves increasing the drive strength of a transmitted digital signal in high-speed digital systems.
FIGS. 2A and 2B
illustrate the difference between traditional digital signal transmissions and pre-emphasized digital signal transmissions. In
FIG. 2A
, the signals shown are transmitted with no pre-emphasis. In
FIG. 2B
, comparative signals are pre-emphasized at each low-to-high or high-to-low transition. As shown here, the pre-emphasis may be strong enough to extend for one entire bit time. If the logic value of the next transmitted signal is the same as the pre-emphasized signal, the driving strength may then be de-emphasized back to normal driving strength. Successive transmissions of the same logic value are typically not pre-emphasized.
While the pre-emphasis of transmitted logic signals as shown in
FIG. 2B
, there may be significant overhead involved with this technique. While pre-emphasizing on every high-to-low and low-to-high transition may improve the data integrity of transmitted signals, power consumption may be increased significantly. Furthermore, while pre-emphasizing some digital signal transmissions may improve data integrity, the practice of pre-emphasizing on each and every transition may not add a significant improvement to data integrity.
SUMMARY OF THE INVENTION
A method and circuitry for pre-emphasizing transmitted logic signals are provided. The method and circuitry may be applied to single-ended center-taped terminated I/O lines, or other types of signal transmission circuitry/mediums suitable for pre-emphasis. In one embodiment, a driver circuit may be configured for monitoring the logic values (i.e. logic 0, logic 1, or logic low, logic high) of signals transmitted by the driver circuit. The driver circuit may compare the logic value of a next logic signal to be transmitted with a first previously transmitted signal and a second previously transmitted signal. Pre-emphasis of the next logic signal may occur based on the logic value of the next logic signal to be transmitted as well as the logic values of the first and second logic signals. If the first and second logic signals have the same logic value, and the next logic signal has a different value, the next logic value may be pre-emphasized. If the next logic signal has a logic value that is equivalent to either the first logic signal or the second logic signal, it may be transmitted without pre-emphasis.
In one embodiment, a driver circuit includes a monitoring circuit, a comparison circuit, and an output circuit. The monitoring circuit may be configured to monitor the logic values, or states, of the logic signals transmitted by the driver circuit. The comparison circuit may be configured to compare the logic values of the recently transmitted logic signals. The comparison circuit may determine whether the next logic signal to be transmitted is to be pre-emphasized or not. The comparison circuit may also include a pre-emphasis controller. The pre-emphasis controller may be coupled to the output circuit, and may be configured to generate either a first or a second enable signal if the next logic signal is to be transmitted with pre-emphasis. If the next logic signal to be transmitted is a logic high signal (or logic one), and is to be pre-emphasized, a first enable signal may be asserted. Similarly, if the next logic signal to be transmitted is a logic low signal (or logic zero) and is to be pre-emphasized, a second enable circuit may be asserted.
In one embodiment, the output buffer may include a first output buffer and a second output buffer. The first and second output buffers may share a common output. During normal (i.e. no pre-emphasis) signal transmissions, the first output buffer may drive the transmitted logic signals, while the second output buffer may remain inactive. During signal transmissions with pre-emphasis, both the first and second output buffers may be active. Since the first and second output buffers share a common output, activating the second output buffer may provide additional drive strength to the transmitted signal, thereby providing the desired pre-emphasis.
Thus, in various embodiments, the method and circuitry for pre-emphasizing transmitted logic signals may allow for high-speed digital signal transmissions with high data integrity. By pre-emphasizing transmitted logic signals only under certain conditions, a significant savings in power consumption may occur.
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“A Scalable 32Gb/s Parallel Data Transceiver with On-Chip Timing Calibration Circuits”, Yang, et al. 2000 IEEE International Solid-State Circuits Conference, Session 15, Paper TP 15.6, pp. 258-259.
“Transmitter Equalization for 4G
Chakrabarti Prabhansu
Jong Jyh-Ming
Yuan Leo
Cho James H
Kivlin B. Noäl
Sun Microsystems Inc.
Tokar Michael
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