Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-09-12
2006-09-12
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S119000, C711S122000, C711S137000, C712S035000, C365S076000, C365S194000
Reexamination Certificate
active
07107401
ABSTRACT:
A method and a digital processor circuit to process digital delays are provided. The digital processor circuit may comprise circuit memory and a processor module such as a digital signal processor (DSP), a delay line module, a filter module and a sample rate converter module. The circuit memory may comprise a digital delay line memory portion to provide a plurality of digital delay lines; and a cache memory portion to perform a pre-fetch data transfer operation from the main memory to the cache memory portion. The cache memory portion may comprise a plurality of delay caches that are updated with data samples from corresponding delay lines in the main memory. The sizes (e.g., the relative sizes) of the delay line memory portion and the cache memory portion of the circuit memory may be adjustable. The sizes may be dependent upon algorithms executed by the processor module.
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Chuan Boon Choong
Savell Thomas C.
Creative Technology Ltd
Padmanabhan Mano
Schwegman Lundberg Woessner & Kluth P.A.
Song Jasmine
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