Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Analysis of complex waves
Reexamination Certificate
2001-04-27
2002-12-10
Oda, Christine (Department: 2858)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
Analysis of complex waves
C326S093000, C341S118000, C341S120000, C327S407000, C324S076590
Reexamination Certificate
active
06492798
ABSTRACT:
The present invention relates, in general, to the testing of circuits and, more specifically, to a method and circuit for testing high-frequency mixed-signal circuits with a low-frequency tester.
BACKGROUND OF THE INVENTION
The number of integrated circuits (ICs) that contain mixed-signal (analog and digital) circuitry is increasing as a percentage of all ICs, and is expected by industry observers to exceed 60% in 2001. The number of digital pins of these ICs is also increasing and can exceed 1000 pins, and the digital data rate applied to the pins is increasing and can exceed 500 MHz. Digital testers that achieve these pin counts and data rates can cost several million dollars. Adding mixed-signal test capability to one of these testers can increase its price by 20% to 40%.
Mixed-signal testers are significantly more expensive than digital testers, primarily for three reasons: (1) a high signal-to-noise ratio (SNR) must be achieved in the presence of many high speed digital signals; (2) the analog stimulus frequencies must be a precise fraction of the digital clock frequencies; and (3) the analog circuitry of the tester must operate at higher speed and accuracy than the circuits to be tested.
The two most common mixed-signal circuits are analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). The accuracy and speed of converters has increased over the years, and can exceed 16 bits at 100 MHz. To test converters, a tester typically needs to be faster and more accurate than the converter being tested, but it is becoming more difficult and expensive for testers to have this performance advantage because tester performance and IC performance are converging as fundamental limits to circuit technology are approached. When testing an ADC or DAC within a larger circuit, an N-bit digital output or input is accessed by the tester as N digital signals in parallel, or serially at a rate equal to N times the sample rate. N is typically between 6 and 16. Testing high frequency (sample rate) DACs and ADCs at their maximum operating speed (“at-speed”) is necessary because their performance typically degrades as operating frequency increases.
It is nevertheless possible to test a DAC or ADC at a clock rate that is much less than the normal operating speed of the ADC or DAC. For example, differential non-linearity (DNL), the maximum difference between the actual voltage step sizes and the ideal step size of a DAC, is commonly measured by providing a digital input value to the DAC; measuring the resulting output voltage, V
1
, for a period long enough to filter out noise; provide a second digital value, higher by one bit, to the DAC; measuring the filtered output voltage, V
2
; calculating V
2
-V
1
; and comparing the calculated value to an ideal value.
Using this sequence, all output voltage differences are measured. However, the DAC is tested at a rate slower than its maximum speed because time must be allowed for a sufficiently accurate measurement of its low-pass filtered output voltage, and, because the output analog voltage increments by only one least significant bit-equivalent at a time, this is much slower than the largest increments that must be converted, which can be more than one half of the 2
N
step full-range.
U.S. Pat. No. 5,825,786, granted to M. Burns on Oct. 20, 1998, for “Undersampling Digital Testability Circuit,” describes a circuit for testing the integrity of high data rate transfers by undersampling the digital input to a DAC being tested, but does not otherwise test the DAC itself. The patent does not teach how to analyze the analog signal output of the DAC to detect defects. Undersampling refers to the technique of sampling a signal at a sample rate that is slower than twice the highest frequency of interest in the sampled signal.
Burns U.S. Pat. Nos. 5,578,935 granted on Nov. 26, 1996, for “Undersampling Digitizer with a Sampling Circuit Positioned on an Integrated Circuit” and 5,589,763 granted on Dec. 31, 1996, for “Coherent Undersampling Digitizer for Use with Automatic Field Test Equipment”, are concerned with the difficulties associated with accurate measurement of high frequency signals using Automated Test Equipment caused by stray capacitance and inductance from the fixturing such as wafer probes, handler contactors and device sockets may have a detrimental effect on the high frequency electrical signals to be measured. Exemplary, the settling time of a palette digital to analog converter (DAC) could be difficult to accurately measure through a long wire since the inductance of this long wire would adversely affect the signal to be measured. The '935 patent proposes incorporating a comparator on the same integrated circuit chip as the circuit under test so that stray capacitance and inductance is minimized if not eliminated. The '763 patent proposes the use of a coherent undersampling digitizer for use with automatic field test equipment. Both patents describe a method for deducing the value of a periodic signal at any instant in its cycle by repeatedly comparing the signal to a reference voltage that successively approximates the signal based on the result of the comparison. The patents do not teach how to generate a high-frequency stimulus for the CUT without using a high frequency tester. Further, the methods require an algorithmic search for each sample's value, which can produce erroneous results in the presence of high frequency noise.
A paper, entitled “Analog DFT Using an Undersampling Technique” published in 1999 in by R. Mason proposes the use of undersampling to allow the observation of high frequency signals via a low frequency on-chip analog bus. An analog switch samples a signal of interest and uses an analog bus as a sample-and-hold capacitor. The sampling switch is controlled by pulses, having a duration, t, and a period, T, under control of a sampling clock, and is used to observe signals with a bandwidth less than 0.5/t, according to Nyquist theory, while conveying signals on the analog bus at frequencies less than 0.5/T. In the paper, 1 MHz sampling clocks having pulses between 2 and 0.5 ns duration were used to observe signals with between 180 MHz and 1.1 GHz bandwidth. The analog bus signal was conveyed off-chip at frequencies below 500 kHz by an analog buffer. The sampling switch used in this paper is a conventional complementary metal oxide semiconductor (CMOS) transmission gate. Mason does not address the fundamental problem of how to generate a high frequency stimulus for the circuit under test. In addition, the technique requires two high frequency signals, the applied signal and a sampling clock whose frequency is only “slightly offset from the sinusoid signal”. For high frequencies, it can be expensive to generate two such frequencies, for example, a 200 MHz sinusoid and a 199.99 MHz square wave, accurately and with low jitter. Further, the technique requires an on-chip hold capacitor, which limits the amount of low pass filtering that can be accomplished with this capacitor to reduce the high frequency noise.
SUMMARY OF THE INVENTION
The present invention seeks to reduce the cost of mixed-signal testers and to simplify high frequency mixed-signal testing by using low frequency stimulus signals; generating and sampling analog signals at a constant low frequency, independently of digital sampling signals used during testing; and facilitating serial data access at rates that are much less than the sampling rate. The present invention also seeks to implement the circuit in a manner that minimizes extra circuitry for circuits constructed according to the IEEE 1149.4 standard.
The term “high frequency” herein refers to the sampling rate or the frequency of the signal input to the device under test. The term “low frequency” refers to the frequencies of signals used to generate the high frequency signal applied to the device under test as well as to the data access rate of the output of the device.
In accordance with the present invention, at least two low frequency signals, each being either an analo
LogicVision, Inc.
Oda Christine
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