Method and circuit for suppressing data loading noise in nonvola

Details Method and circuit for suppressing data loading noise in nonvola Method and circuit for suppressing data loading noise in nonvola

1995-02-21

1996-07-30

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Noise suppression

36515905, 365194, G11C 700

Patent

active

055418848

ABSTRACT:
In a nonvolatile memory comprising a data amplifying unit and an output element mutually connected by a connection line, the noise suppressing circuit comprises a network for generating a noise suppressing signal which is synchronized substantially perfectly with a signal controlling data loading from the amplifying unit to the output unit, presents a very short duration, equal to the switching time of the output unit, and freezes the amplifying unit during switching of the output unit to prevent this from altering the data stored in the amplifying unit or internal circuits of the memory. The same signal also blocks an address amplifying unit on the address bus.

REFERENCES:
patent: 4339809 (1982-07-01), Stewart
patent: 4827454 (1989-05-01), Okazaki
patent: 4943949 (1990-07-01), Yamaguchi et al.
patent: 5272674 (1993-12-01), Pathak et al.
patent: 5341338 (1994-08-01), Hashiguchi et al.

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