Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2005-06-07
2005-06-07
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S745000
Reexamination Certificate
active
06904551
ABSTRACT:
A method and circuit thereof for performing setup and hold (SUAH) testing on integrated circuits including, but not limited to SRAM, utilizing a relatively low number of test vectors, obviating the conventional requirement of writing to and reading back from each and every memory address. In one embodiment, a first test data signal of all zeros (0) is inputted to the input stage of the SRAM under test, and a subsequent second data signal of all ones (1) follows. In one embodiment, XOR/XNOR gates detect differences in data signals between the inputs and outputs of input stage latches/registers after clocking. In one embodiment, detected differences are combined into an error signal in combinational logic. In one embodiment, error signals are exported serially to a test system by a scan chain. Alternatively, in another embodiment, error signals are exported in parallel via individual output drivers.
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Cypress Semiconductor Corporation
Lamarre Guy J.
Wagner , Murabito & Hao LLP
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