Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-01-10
2003-05-27
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06571382
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related generally to the field of programmable logic devices and more particularly to an improved method and circuit for programming a programmable logic device, particularly an in-system programming (“ISP”)-compatible programmable logic device.
BACKGROUND OF THE INVENTION
Reprogrammable logic devices provide the ability to program a device to perform one function, then alter or replace that function by reprogramming the device. Volatile reprogrammable devices lose their programmed functionality when powered off, whereupon they move to a default state with all output drivers placed in a high-impedance mode. Non-volatile devices retain their programmed functionality until erased and reprogrammed, regardless of power availability. In devices that retain their functionality after power-down (e.g., long term stable devices such as Complex Programmable Logic Devices (“CPLDs”) available from Xilinx, Inc., assignee of the present invention), there is a possibility that a power interruption during erasing or programming can lead to an incorrectly programmed device incapable of operating properly, of being deactivated, or of being reprogrammed to its proper function, due to the dysfunctional state in which the device is left after the interrupted programming cycle. This possibility is especially risky for devices programmed outside a controlled environment dedicated to the reprogramming function.
In-System Programming (“ISP”)-enabled devices are often programmed within the system in which they normally function (e.g., as a substitute for an application specific integrated circuit (“ASIC”) within a network appliance), instead of within a dedicated programming apparatus. While the potential loss from the unlikely event of a power interruption during programming is minimal where the device need be simply disposed of and a replacement obtained and programmed in its place, the potential loss of time and effort for repairs is far greater where the device is integrated within a multi-component, remote-programmable system at the time of programming, as is often the case with an ISP-enabled device. Thus, while ISP-enabled devices are highly advantageous in enabling remote upgrade of hardware systems, even over wide area networks such as the Internet, if an ISP-enabled device's programming cycle is interrupted by a power failure or other malfunction and the interruption results in device dysfunction, that dysfunction may render an entire device, system or network incapable of re-initializing. Moreover, where a system is remotely programmed due to access difficulty issues, the cost of having to dismantle the system to replace the programmable device can be quite high. It is therefore desirable to substantially reduce or eliminate the risk that a reprogrammable device will be rendered dysfunctional or unusable by an ill-timed power lapse or similar complication during device programming.
To understand how the invention addresses this need, it will be useful to explain the basic elements of non-volatile device reprogramming. Although this description applies particularly to CPLDs available from Xilinx®, Inc., assignee of the invention, the programming sequence applies generally to any available non-volatile programmable device, as will be understood by those skilled in the art to which the invention pertains. Most CPLD devices are programmed (that is, they store their programming information) with a non-volatile means such as EPROM cells or flash transistors. EPROM programming involves raising voltages at certain transistor gates to a high level and maintaining the high level until sufficient charge has flowed onto or away from a floating gate of the transistor to cause the transistor to maintain a certain state when the high voltage is removed. Typically, a stream of programming and other data (a “bitstream”) several thousand bits long can be shifted into several devices in less time than is required to program a single non-volatile transistor in a device. Thus, a practical and widely used programming procedure is to serially shift a programming instruction and a unit of data to be programmed, and then move into a programming mode during which all addressed cells are programmed simultaneously, as specified by the programming data. This sequence is repeated (absent the shifting-in of the programming instruction) until all cells in the device are programmed. Design synthesis software is normally used to create the programming bitstream used to configure the device or devices.
The period of time required to shift programming data into and program such devices increases their susceptibility to programming interruption via random power loss or other complications. For example, referring to
FIG. 1
, an ISP-enabled CPLD
10
is typically wired into a system
20
including a microprocessor
12
and an external memory unit
14
, with a common bus
16
shared by the three integrated circuit devices on board
8
. If power to CPLD
10
is interrupted during reprogramming, a partially or incorrectly programmed CPLD could irretrievably tie up common bus
16
, particularly if the output drivers of CPLD
10
are stuck in an active mode driving a high current, thereby rendering dysfunctional all of board
8
, and potentially all of system
20
and any network to which it might be attached.
There is therefore a need in the art for a method and system for safely reprogramming in-system, reprogrammable logic devices.
SUMMARY OF THE INVENTION
To address the shortcomings of the available art, the present invention provides a method and system for reducing the likelihood of reprogrammable device programming errors, particularly those caused by power interruptions, by reducing the time within which such interruptions can result in system errors. To this end, the programming data bitstream is configured such that all elements controlling the device outputs (controlled by output enable or “OE” bits) are set to a high impedance (tristate) mode at or near the beginning of the programming process and are programmed at or near the end of the process, thereby reducing or minimizing the amount of time the device is vulnerable to power outages that might result in an unknown output-driving condition.
An alternative embodiment further comprises defining a single bit in the programming data bitstream as a single I/O enable bit, whereby the device output drivers remain in a high-impedance mode until the I/O enable bit is received. By providing the device with this critical I/O enable bit near the end of the programming bitstream, the amount of time the device remains vulnerable to power loss is further decreased.
In yet another embodiment, a still additional mechanism for reducing risk is provided, comprising a current sensor circuit integrated with device I/O circuitry, for sensing high output current and deactivating the I/O circuitry where high current is sensed but not expected.
REFERENCES:
patent: 5815405 (1998-09-01), Jones et al.
patent: 5862365 (1999-01-01), Modo et al.
patent: 5946478 (1999-08-01), Lawman
patent: 6205574 (2001-03-01), Dellinger et al.
Jacobson Neil G.
Murphy Matthew T.
Bowers Brandon
Hirsch Lorraine
Siek Vuthe
Tachner Adam H.
Xilinx , Inc.
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