Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-11-25
2001-07-24
Beausoleil, Robert (Department: 2785)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S024000, C713S340000
Reexamination Certificate
active
06266786
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer technology, and more particularly, to a method and circuit for safeguarding the data stored in a CMOS RAM (Complementary Metal-Oxide Semiconductor Random Access Memory) in a computer system, such as an IBM-compatible personal computer (PC), when the battery unit used to power the CMOS RAM is below working level.
2. Description of Related Art
CMOS RAMs are a volatile memory made using CMOS technology, which are characterized in low power consumption and are therefore widely used as the storage means for BIOS (Basic Input Output Systems) setup data and real-time clock in PCs. A CMOS RAM unit in a PC is typically from 128 to 256 bytes in capacity.
In a PC, the CMOS RAM is typically powered alternatively by two sources: a main power supply and a battery unit, in such a manner that when the PC is powered on, the CMOS RAM is powered by the main power supply, and when powered off, the CMOS RAM is powered by the battery unit. The battery unit is typically a nonrechargeable type. For the purpose of environmental protection, the US regulations specifically set forth the use of lithium battery as the battery for CMOS RAM in PCs. When the PC is powered off, the data stored in the CMOS RAM can still be retained since it is still powered by the battery. When the PC is powered on, the power connection to the CMOS RAM will be switched from the battery to the main power supply for the purpose of saving battery power.
FIG. 1
is a schematic diagram showing a typical power supply system for a CMOS RAM unit
100
in a PC. As shown, the CMOS RAM
100
is connected via a first diode D
1
to the main supply V
CC
of the PC, and via a second diode D
2
to a battery unit, which is typically a nonrechargeable lithium battery unit supplying a battery power VBAT, where VBAT is less in magnitude than V
CC
. When the PC is powered on, the main power V
CC
is transferred to the CMOS RAM
100
. In this case, since V
CC
is greater in magnitude than VBAT, the second diode D
2
is reversely biased, and thus the battery voltage VBAT is inhibited by the second diode D
2
. However, when the PC is powered off, the second diode D
2
is fowardly biased, thus allowing the battery voltage VBAT to be transferred to the CMOS RAM
100
.
One drawback to the foregoing system, however, is that the battery unit is non-rechargeable and therefore will be consumed up over time. When the battery power is below working level, it has to be replaced by a new one. When doing this, the data stored in the CMOS RAM
100
can be permanently lost. Therefore, each time the old battery is replaced, the user has to redo the previous settings to the PC, which is quite inconvenient to the user and may cause some data to be lost forever.
In modern PCs, the CMOS RAM is also used to store some important initialization data of the operating system (OS) in addition to BIOS setup data. Therefore, once the data stored in the CMOS RAM are lost, it would be extremely difficult and laborious to put the PC back to work.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method and circuit for safeguarding CMOS RAM data in a computer system at low battery power so that the CMOS RAM data would not be lost when the system battery is below working level.
In accordance with the foregoing and other objectives of the present invention, a method and circuit for safeguarding CMOS RAM data in a computer system is provided.
By the method of the invention, when the PC is powered off, the current power level of the battery unit is detected to see whether it is below working level; if yes, the main power of the PC is turned on; the data currently stored in the CMOS RAM unit are moved to a backup-data storage unit such as the hard disk; and after this, the main power is turned off again. At the next time the PC is powered on, the data currently stored in the backup-data storage unit are moved back to the CMOS RAM unit; and after this, a message is displaying on the monitor screen, requesting the user to replace the battery unit for the CMOS RAM unit with a new one.
The CMOS RAM data safeguarding circuit of the invention is designed for use on a computer system of the type having a power supply capable of generating a main power and a standby power and a CMOS RAM unit powered by a battery unit when the computer system is powered off and by the main power from the power supply when the computer system is power on. The circuit of the invention includes a battery power detector, which is powered by the standby power from the power supply when the computer system is powered off, for detecting whether the battery power from the battery unit is below working level; if yes, the battery power detector generating a backup request signal. Moreover, the circuit of the invention includes a main control unit, which is powered by the main power from the power supply when the computer system is powered on and by the standby power from the same power supply when the computer system is powered off, capable of, when activated by the backup request signal from the battery power detector, moving the data currently stored in the CMOS RAM unit to a backup-data storage unit, such as the hard disk. Thereafter, at the next time the computer system is powered on, the main control unit moves the backup data from the backup-data storage unit back to the CMOS RAM unit. In this manner, the CMOS RAM data are safeguarded from losing at low battery power.
REFERENCES:
patent: 4965738 (1990-10-01), Bauer et al.
patent: 5315161 (1994-05-01), Robinson et al.
patent: 5884084 (1999-03-01), Nelson et al.
patent: 6041413 (2000-03-01), Wang
Intel Corporation, ATX Specification Version 2.01, pp.1-27, Feb. 1997.
Baderman Scott
Beausoleil Robert
Huang Jiawei
Patents J. C.
VIA Technologies Inc.
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