Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
1999-02-24
2001-11-20
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S189090, C365S226000, C365S189050
Reexamination Certificate
active
06320797
ABSTRACT:
TECHNICAL FIELD
The present invention relates to voltage generating circuits, and, more particularly, to a method and circuit for regulating a charge pump circuit to minimize the ripple and the power consumption of the charge pump circuit.
BACKGROUND OF THE INVENTION
In many electronic circuits, charge pump circuits are utilized to generate a positive pumped voltage having an amplitude greater than that of a positive supply voltage, or to generate a negative pumped voltage from the positive supply voltage, as understood by those skilled in the art. For example, in a conventional dynamic random access memory (“DRAM”), a charge pump circuit may be utilized to generate a boosted word line voltage V
CCP
having an amplitude greater than the amplitude of a positive supply voltage V
CC
, and a negative voltage pump circuit may be utilized to generate a negative substrate or back-bias voltage V
bb
that is applied to the bodies of NMOS transistors in the DRAM. Another typical application of a charge pump circuit is the generation of a high voltage utilized to erase data stored in blocks of memory cells or to program data into memory cells in non-volatile electrically block-erasable or “FLASH” memories, as will be understood by those skilled in the art.
FIG. 1
is a schematic of a conventional two-stage charge pump circuit
100
that generates a pumped output voltage V
P
having an amplitude greater than the amplitude of a supply voltage source V
CC
in response to complementary clock signals CLK and {overscore (CLK)}, as will be described in more detail below. The charge pump circuit
100
includes two voltage-boosting stages
102
and
104
connected in series between an input voltage node
106
and an output voltage node
108
. The voltage-boosting stage
102
includes a capacitor
110
receiving the clock signal CLK on a first terminal and having a second terminal coupled to the input node
106
. A diode-coupled transistor
112
is coupled between the input voltage node
106
and a voltage node
114
, and operates as a unidirectional switch to transfer charge stored on the capacitor
110
to a capacitor
116
in the second voltage-boosting stage
104
. The capacitor
116
is clocked by the complementary clock signal {overscore (CLK)}. A transistor
118
transfers charge stored on the capacitor
116
to a load capacitor C
L
when the transistor
118
is activated. A threshold voltage cancellation circuit
122
generates a boosted gate signal V
BG
responsive to the CLK and {overscore (CLK)} signals, and applies the signal V
BG
to control activation of the transistor
118
. When the CLK and {overscore (CLK)} signals are high and low, respectively, the circuit
122
drives the signal V
BG
low to turn OFF the transistor
118
, and when the CLK and {overscore (CLK)} signals are low and high, respectively, the circuit
122
drives the signal V
BG
high to turn ON the transistor
118
. The cancellation circuit
122
may be formed from conventional circuitry that is understood by those skilled in the art. The charge pump circuit
100
further includes a diode-coupled transistor
120
coupled between the supply voltage source V
CC
and node
106
. The diode-coupled transistor
120
operates as a unidirectional switch to transfer charge from the supply voltage source V
CC
to the capacitor
110
.
A ring oscillator
124
generates an oscillator clock signal OCLK that is applied to a switching circuit
126
coupled between the ring oscillator
124
and a clocking-latching circuit
128
. The switching circuit
126
receives a regulation output signal REGOUT from external control circuitry (not shown in FIG.
1
), and when the REGOUT signal is inactive low, the switching circuit
126
presents a low impedance and thereby applies the OCLK signal to the clocking-latching circuit
128
. When the REGOUT signal is active high, the switching circuit
126
presents a high impedance, which isolates or removes the OCLK signal from the clocking-latching circuit
128
. The clocking-latching circuit
128
latches the applied OCLK signal and generates the complementary clock signals CLK and {overscore (CLK)} responsive to the latched OCLK signal. The CLK and {overscore (CLK)} signals have the same frequency as the OCLK signal, and are complementary signals so there is a phase shift of 180° between these signals.
The operation of the conventional charge pump circuit
100
will now be described in more detail with reference to the timing diagram of
FIG. 2
, which illustrates the voltages at various points in the charge pump circuit
100
during operation. In operation, the charge pump circuit
100
operates in two modes, a normal mode and a power-savings mode. During both the normal and power-savings modes of operation, the ring oscillator
124
continuously generates the OCLK signal. The charge pump circuit
100
operates in the normal mode when the pumped output voltage V
P
is less than a desired pumped output voltage V
PD
. When V
P
<V
PD
, the external control circuitry drives the REGOUT signal inactive low causing the switching circuit
126
to apply the OCLK signal to the clocking-latching circuit
128
. In response to the applied OCLK signal, the clocking-latching circuit
128
latches the OCLK and clocks the stages
102
and
104
with the CLK and {overscore (CLK)} signals generated in response to the latched OCLK signal.
At just before a time t
0
, the CLK signal is low having a voltage of approximately 0 volts and the {overscore (CLK)} signal is high having a voltage of approximately the supply voltage V
CC
, and each of the voltages on the nodes
106
,
114
, and
108
and the have assumed values as shown for the sake of example. Also, before the time t
0
the REGOUT signal is inactive low and the circuit
122
drives the boosted gate signal V
BG
high responsive to the CLK and {overscore (CLK)} signals being low and high, respectively. When the CLK signal is low, the terminal of the capacitor
110
is accordingly at approximately ground and the voltage at the node
106
is sufficiently low to turn ON the diode-coupled transistor
120
, transferring charge from the supply voltage source VCC through the transistor
120
to charge the capacitor
110
. As shown in
FIG. 2
, the voltage at the node
106
(i.e., the voltage across the capacitor
110
) is increasing just before the time t
0
as the capacitor
110
is being charged. Also just before the time t
0
, the voltage at the node
114
equals the high voltage of the {overscore (CLK)} signal plus the voltage stored across the capacitor
116
(V
116
). This bootstrapped voltage on the node
114
is sufficiently greater than the voltage V
p
on the output voltage node
108
to turn ON the transistor
118
, transferring charge from the capacitor
116
through the transistor
118
to the load capacitor C
L
. As shown, the voltage at node
114
is decreasing and the voltage V
p
increasing just before the time to as charge is being transferred through the transistor
118
.
At the time t
0
, the CLK signal goes high, driving the voltage on the node
106
to the high voltage (V
CC
) of the CLK signal plus the voltage stored across the capacitor
110
(V
110
). At this point, the voltage on the node
106
is sufficiently high to turn OFF the transistor
120
, isolating the node
106
from the supply voltage source V
CC
. Also at the time t
0
, the {overscore (CLK)} signal goes low (to ground), causing the voltage on the node
114
to equal the voltage V
116
stored across the capacitor
116
. The voltage on the node
106
is now sufficiently greater than the voltage on the node
114
to turn ON the transistor
112
, transferring charge from the capacitor
110
through the transistor
112
to the capacitor
116
. As shown in
FIG. 2
, between the time t
0
and a time t
1
, which corresponds to the interval the CLK signal is high and {overscore (CLK)} signal is low, the voltage at the node
106
decreases and the voltage at the node
114
increases as charge is pumped or transferred through the transistor
112
. It should be noted that during this ti
Dorsey & Whitney LLP
Elms Richard
Micro)n Technology, Inc.
Nguyen Tuan
LandOfFree
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