Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Reexamination Certificate
1998-06-05
2001-02-06
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Output switching noise reduction
C326S083000, C326S086000
Reexamination Certificate
active
06184703
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to digital circuits. More particularly, it relates to an output buffer including control circuits for reducing power and/or ground bounce noise.
Digital logic circuits are widely used in the areas of electronics and computer-type equipment. One such use of digital logic circuits is to provide an interface function between one logic type (i.e., CMOS) of one integrated circuit device and another logic type (i.e., TTL) of another integrated circuit device. An output buffer is an important component for performing this interface function. The output buffer generates, when enabled, an output signal that is a function of a data input signal received from other logic circuitry of the integrated circuit.
An output buffer circuit typically uses a pull-up and a pull-down field-effect transistor coupled in series between first and second power supply terminals. The first power supply terminal may be supplied with a positive potential which is coupled to an internal power supply potential node. The second power supply terminal may be supplied with a ground potential, which is coupled to an internal ground potential node. The connection point of the pull-up and pull-down field-effect transistors is further joined to an output terminal.
Dependent upon the logic state of the data input signal and an enable signal, either the pull-up or pull-down field-effect transistor is quickly turned on and the other transistor is turned off. Such rapid switching, on and off, of the pull-up and pull-down field-effect transistors causes sudden surges of current which create what is commonly known as current spikes. These current spikes flow through the impedance and inductive components of power supply lines and cause inductive noise at the internal power supply potential and the internal ground potential nodes of the output buffer. In particular, when the pull-down transistor is quickly turned on, a large instantaneous current cooperates with the line inductance to pull up the internal ground potential. This phenomenon is referred to as “ground bounce” noise. Similarly, when the pull-up transistor is quickly turned on, there may be “power bounce” noise on the internal power potential.
Therefore, it is desirable to provide a control circuit which limits the output current of the output buffer during transitions between logic states to reduce ground and/or power bounce noise, but yet maintains a high speed of operation. Further, it is desirable that the output buffer meets the DC specifications, such as the high output voltage (VOH) and the low output voltage (VOL) specifications.
SUMMARY OF THE INVENTION
The present invention is an output buffer that includes control circuits for reducing the amount of ground or power bounce noise, or both. The output buffer includes a driver circuit having one or more driver devices. One such driver circuit is a push-pull circuit having a pull-up and a pull-down driver coupled in series between two power supply terminals. In the present invention, the output current of the driver devices is limited to reduce ground or power bounce noise, or both.
In one embodiment of the present invention, the output current of the driver devices is limited by providing intermediate voltages to the control electrodes of the driver devices. The data input signal is provided to the input of a pass device (or a transmission gate) within the control circuit. At least one control node of the pass device can be coupled to an intermediate voltage that is between the voltages of the power supply terminals. The pass device limits the drive voltage to the driver device (to approximately the value of the intermediate voltage) and results in less output drive current, thus reducing bounce noise. Additionally, the intermediate voltage at the control node causes the pass device to operate as a variable resistive device, which correspondingly limits the slew rate of the drive voltage to the driver device. The slew rate limited drive voltage also limits the slew rate of the output current, further reducing in the amount of bounce noise.
The control circuit for the pull-down driver can be operated to reduce the amount of ground bounce noise. Similarly, the control circuit for the pull-up driver can be operated to reduce the amount of power bounce noise. The output buffer can include control circuits for reducing ground bounce, power bounce, or both ground and power bounce noise.
In one aspect of the present invention, the control circuit accepts a feedback signal from the output of the output buffer. When the drive of the pass device is reduced (to limit the output current) and upon transition of the output to a new logic state, the new logic value is fed back to the control circuit and used to change the operating state of the pass device. This feedback mechanism allows control over the amount of reduction in bounce noise and ensures that the output voltage of the output buffer meets the output VOL and VOH specifications.
In another aspect of the present invention, the control circuit is only turned on during a logic transition (e.g., logic low to logic high, or logic high to logic low) and only for the driver device which is being turned on. The slew rate limitation is not enabled when the driver is turned off. This feature reduces the time both pull-up and pull-down drivers are simultaneously turned on.
In one set of embodiments, the output current control feature is incorporated into the design of the output buffer. In another set of embodiments, the output current control feature is provided by a SLEW control signal that provides for programmability of the inventive feature.
For a further understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.
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Costello John C.
Reese Dirk A.
Vest William B.
Wong Myron W.
Altera Corporation
Le Don Phu
Tokar Michael
Townsend and Townsend / and Crew LLP
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