Method and circuit for rapidly equilibrating paired digit lines

Details Method and circuit for rapidly equilibrating paired digit lines Method and circuit for rapidly equilibrating paired digit lines

1996-11-14

1998-03-24

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

365200, 3652306, G11C 700

Patent

active

057320330

ABSTRACT:
A method and circuit for rapidly equilibrating paired digit lines of the memory array of a dynamic random access memory device during testing of the memory device includes a plurality of pass gates which are used to connect the equilibrating voltage directly to the paired digit lines, bypassing the conventional equilibration circuitry of the memory device. The pass gates used are contained in spare rows of the memory array and are fabricated as part of the memory device. The pass gates are enabled by activating the row lines for the spare rows while the memory device is being operated in a test mode.

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