Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2003-05-08
2004-12-07
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S033000, C333S017300
Reexamination Certificate
active
06828820
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and a circuit for producing a control signal for impedance matching, and more particularly to the method and the circuit for producing the stable control signal for impedance matching by using a count value output from an up-down counter as a control signal for impedance matching to be used for matching of terminating impedance of an impedance matching circuit that requires impedance matching and by comparing a voltage to be compared to be produced based on the count value and changing the count value through control of the up-down counter according to a result from the comparison.
The present application claims priority of Japanese Patent Application No. 2002-132552 filed on May 8, 2002, which is hereby incorporated by reference.
2. Description of the Related Art
Conventionally, an electronic signal transmitting path is provided with a unit which can perform impedance matching at a sending end and at a receiving end of a signal. An aim of performing such impedance matching is to normally transmit an electric signal from the sending end of the signal to the receiving end of the signal. Particularly, some high-speed input/output interfaces constructed using semiconductor devices, since they generate high heat therein, are cooled to minus several tens of degrees. When these high-speed input/output interfaces are used during long periods in communication applications, their temperatures are increased up to plus several tens of degrees. If such the big change in the temperature or power source voltages occurs during use of the high-speed input/output interface, a change also occurs in impedance in the semiconductor device which is performing impedance matching. Due to this, a state occurs in which the impedance in the high-speed input/output interface is not matched and, therefore, a method to avoid such the state and to always maintain a matched impedance is needed. As one of the methods for achieving such the impedance matching, an output impedance calibrating circuit is disclosed in Japanese Patent Application Laid-open No. 2000-59202 (hereinafter referred to a “first application”).
FIG. 30
shows a schematic block diagram of the disclosed output impedance calibrating circuit.
An outline of the disclosed output impedance calibrating circuit is described below. An impedance varying circuit
111
shown in
FIG. 30
provides an impedance according to a binary code output from an up-down counter
114
. A connecting point
111
a
is a connecting point placed between the impedance varying circuit
111
and a resistor
112
. A voltage Va to be compared occurring at the connecting point
111
a
is fed to one input terminal of a comparator
113
. The voltage Va to be compared is a voltage which represents, in a simulated manner, an impedance provided by the impedance calibrating circuit in the high-speed input/output interface. To another input terminal of the comparator
113
is fed a reference voltage Vref which does not change even if a change in temperature occurs. A comparison between the voltage Va to be compared and the reference voltage Vref is made by the comparator
113
and a counting operation corresponding to a result of the comparison is performed in the up-down counter
114
.
Though an impedance in the impedance varying circuit
111
is calibrated according to a binary code output from the up-down counter
114
and feed-back control is exerted so that the voltage Va to be compared converges to the reference voltage Vref, the voltage Va to be compared, as shown in
FIG. 31A
, changes at levels being higher or lower than a level of the reference voltage Vref. That is, the binary code itself output from the up-down counter
114
is changed. Therefore, since the binary code output from the up-down counter
114
, as is, cannot be used as data for impedance matching, conventionally, in order to stabilize the variable binary code so as to be stable and to be a constant value, an averaging circuit (explained later) is introduced.
FIG. 31B
shows a state of a change in a voltage Va to be compared in the case of using such the averaging circuit.
As one of examples of the averaging circuit, technology containing the averaging circuit is disclosed in Japanese Patent Application Laid-open No. Hei 10-190642 (hereinafter called a “second application”). The technology disclosed in the second application is a bit synchronizing technology which is essential when a digital signal in digital transmission is reproduced on a receiving side, in which the averaging circuit is used. The bit synchronizing circuit (not shown) employed in the second application includes a phase comparing unit (not shown), a retiming unit (not shown), an averaging unit (not shown), and a selecting unit (not shown) as elements featuring the bit synchronizing technology.
An outline of operations of the bit synchronizing circuit (not shown) is described. In its phase comparing unit, frequency-divided data obtained by dividing a frequency of receiving data is compared with each clock signal of polyphase clock signals and a specified signal to specify one clock signal contained in the polyphase clock signals having a phase relation being predetermined in the frequency-divided data is produced. The retiming unit (not shown) performs retiming operations on the frequency-divided data according to an extracted clock signal selected by the selecting unit (not shown). The specified signal fed from the phase comparing unit (not shown) to the averaging circuit (not shown) is averaged in synchronization with a signal output from the retiming unit (not shown) and then is output. The selecting unit (not shown) receiving the signal from the averaging unit (not shown) alternatively extracts one clock signal contained in the above polyphase clock signals according to the signal output from the averaging (not shown) unit and outputs the extracted clock signal. The extracted clock signal outputted from the selecting unit (not shown) is used in the retiming unit (not shown) and for performing retiming operations on received data.
The averaging circuit (not shown) disclosed in the above second application is, more particularly, made up of a subtractor, one m-th weighting section, an adder, a storing section, numeral operating section, and a flip-flop (none being shown). The averaging circuit (not shown), after having subtracted, using the subtractor (not shown), a value of the specified signal fed from the phase comparing (not shown) unit from a value fed from the storing section (not shown), performs dividing operations on the subtracted value using the one m-th weighting section (not shown) and stores an average value obtained by adding, using the adder (not shown), a value resulting from the dividing operations to a value fed from the storing section (not shown) and by making a correction to a result from the addition, in the storing section (not shown). Then, a numerical operating section (not shown) rounds off the average value fed from the storing section (not shown) to the nearest integer and the flip-flop (not shown) performs retiming operations on the average value of a phase comparing signal according to a signal fed from the retiming unit and outputs the resulting value.
However, the above conventional technology has problem. That is, as described above, by connecting the above averaging circuit (not shown) to an output terminal of the output impedance calibrating circuit (not shown), a variable binary code can be stabilized. The stabilization of the binary code, in the output impedance calibrating circuit (not shown), can be achieved so long as a voltage Va to be compared is changed at a level being sufficiently apart from an offset voltage of the comparator
113
from a level of the reference voltage Vref. This is because, as shown in
FIG. 31A
, the voltage Va to be compared is changed under such conditions described above at two voltage level being higher and lower than a level of the reference voltage Vref. Moreover, an offset
Cho James H.
NEC Electronics Corporation
Ostrolenk Faber Gerb & Soffen, LLP
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