Method and circuit for precise timing of signals in an...

Details Method and circuit for precise timing of signals in an... Method and circuit for precise timing of signals in an...

2005-09-13

2005-09-13

Lam, David (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S225700

Reexamination Certificate

active

06944090

ABSTRACT:
A method and circuit for timing the start of a precharge period in an eDRAM. The circuit including: a delayed lock loop circuit for receiving a clock signal and generating a control signal for adjusting an internal delay of the clock signal; and means for generating a delayed clock signal in response to the control signal. The means for generating the delayed clock signal is a multiple stage delay circuit, each stage of the multiple delay stage circuit connected in series and each stage individually responsive to the control signal.

REFERENCES:
patent: 5663921 (1997-09-01), Pascucci et al.

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