Method and circuit for performing 3/5 major voting

Details Method and circuit for performing 3/5 major voting Method and circuit for performing 3/5 major voting

1997-06-09

2002-06-25

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S797000

Reexamination Certificate

active

06412094

ABSTRACT:

BACKGROUND OF THE INVENTION
In the TACS/AMPS mobile phone system every base station sends a continous stream of data on at least one of the twenty-one dedicated forward control channels (FCC). Each frame of the data stream contains bit sync and word sync for mobiles to obtain synchronisation. B/I bits (Busy/Idle bits) are sent at the beginning of every bit sync sequence, word sync sequence, first repeat of the word and every ten message bits thereafter to indicate the state of the reverse channel. The information is sent in forty-bit words and every word is repeated five times to give adequate error protection against fading. As the previous message is sent the following message will be sent also repeated five times preceded by bit sync and word sync. Also the words transmitted on the reverse control channel (RCC) and reverse voice channel (RVC) are repeated five times, whereas the words transmitted on the forward voice channel (FVC) are repeated eleven times. These channels (RCC, RVC, FVC) do not consist of a continously transmitted data stream as does the forward control channel (FCC). At reception major voting is performed on the received bit stream to determine whether the recepted bit has the value one or zero. Major voting is usually performed by saving every repeat in a memory bit by bit, and when the bits from all repeats are saved in a memory, each bit is given the value one or zero according to which value appeared more often, i.e. which value appeared at least three out of five times. The drawback of this method is that it requires a large memory for being able to save all five repeats. Major voting may be performed by logic circuits in which case the bits may be saved in registers or by microprocessors in which the voting algorithm is stored, in which case the bits may be stored in RAM. The memories have to be reset before receiving the following data stream and therefore continous voting has not been realized.
The main objective of the present invention is thus to provide a method and circuit by which 3/5 major voting may be performed with considerably less memory as compared to prior art, and continously which means that a stream of bits may be received without interruption.
SUMMARY OF THE INVENTION
According to the invention major voting is performed by calculating the appeared number of either ones or zeros at every bit of the five repeats and by deciding according to this calculation whether the value of a bit is one or zero. The number of ones or zeros is counted only to three as this number is adequate for performing the voting. Even if the bit has, for an example the value one in all five repeats, it is enough to register three received ones when counting ones, as it is the majority of five and therefore the voting result is the same as if the calculation would be performed to five, i.e. the voting result is one. The situation is equivalent when zeros are counted. The voting according to the method of the present invention may therefore be performed by counting either ones or zeros but not both. In this method a lot of memory is saved because not all the received bits are saved, only the number of received ones or zeros. Because the number of ones/zeros from five repeats is counted to three and the number is expressed as a binary number, it is adequate to have two memory positions, i.e. two bits for the voting of each bit. It is to be noted that although the number of bits of one value (ones or zeros) is counted only to three for every bit position, still every incoming bit is checked. When three bits of the value that is being counted (ones or zeros) have been received the checking of incoming bits is still continued, but this does not affect the calculation any more, because the major value has already been reached. One bit, the least significant bit (LSB) has the weight two to the power of zero, and the other bit, the most significant bit (MSB) has the weight two to the power of one. In prior art five bits have to be saved for the voting of each bit, whereas now two bits are adequate because only the number of received ones or zeros for each bit is saved as a two-bit binary number. The voting method may be performed by a logic circuit so that the voting result is achieved quickly and voting may be performed continously. The invention is characterized by what is stated in the characterizing part of claim
1
.


REFERENCES:
patent: 3760371 (1973-09-01), Pitroda et al.
patent: 3919690 (1975-11-01), Field et al.
patent: 4132975 (1979-01-01), Koike
patent: 4134103 (1979-01-01), Huxtable et al.
patent: 4400811 (1983-08-01), Brown et al.
patent: 4404677 (1983-09-01), Grande et al.
patent: 4577332 (1986-03-01), Brenig
patent: 4617475 (1986-10-01), Reinschmitt
patent: 4670880 (1987-06-01), Jitsukawa et al.
patent: 4937843 (1990-06-01), Takemoto
patent: 5241548 (1993-08-01), Dillon et al.

Affiliated with

Also associated with

Rating

Method and circuit for performing 3/5 major voting does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and circuit for performing 3/5 major voting, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and circuit for performing 3/5 major voting will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2911804