Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-18
2002-01-08
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C327S545000, C327S585000
Reexamination Certificate
active
06337502
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the manufacture of semiconductor products in general.
BACKGROUND OF THE INVENTION
During the manufacture of semiconductor products, layers of material are laid down or grown. Some layers are then etched, to produce the desired shapes of transistors, metal lines, and other microelectronics devices. When the processing has finished, a functioning chip is produced. If the chip contains a memory array, it will have a plurality of memory transistors which can be programmed to store charge (and, possibly, erased also). For example, the memory transistors might be floating gate transistors, nitride read only memory (NROM) transistors, silicon oxide-nitride oxide-silicon (SONOS) transistors and all other non-volatile memory metal oxide semiconductor (MOS) devices that can store charge.
Unfortunately, the manufacturing process can have some undesired side effects. For example, in MOS technology, the charging of active elements during the manufacturing process may alter the device's characteristics or even damage them.
FIG. 1
, to which reference is now made, shows a typical cross-section of an MOS or complementary MOS (CMOS) transistor. It is typically formed of a gate oxide
10
over which is a polysilicon element
12
. On either side of the gate oxide
10
are field oxides
14
which are much thicker than the gate oxide
10
. Typically, the polysilicon element
12
also spreads over the field oxides
14
.
During manufacture, the field oxides
14
are first produced on a substrate
8
, after which the gate oxides
10
are grown. A layer of polysilicon is laid over the oxides
10
and
14
which is then etched to the desired shapes, with the help of a shaped photoresist layer
15
. The etching process typically involves placing a plasma
16
between the chip and an electrified plate
18
connected to a high voltage and electrically connecting a second electrified plate
20
to the substrate
8
.
During etching, the edges of the polysilicon elements become exposed to the etching environment. Since the plasma
16
is ionized and since polysilicon is a conductive material, the polysilicon element
12
becomes charged. This is known as the “charging effect”. The more charge the polysilicon element
12
attracts, the greater the voltage drop between the polysilicon element
12
and the substrate
8
. If the voltage drop is high enough, it will induce Fowler-Nordheim (F-N) tunneling of charge from the substrate
8
to
20
the polysilicon element
12
, via the gate oxide
10
. This is indicated by the arrows
24
. Since the field oxides
14
are quite thick, no F-N tunneling occurs through them. Unfortunately, F-N tunneling causes breakdown of the gate oxide
10
, especially if the gate oxide
10
is quite thin, as is becoming increasingly common. It will be appreciated that, once the gate oxide
10
has broken down, the transistor will not function.
The extent of the F-N tunneling is a function of the size of the polysilicon element
12
, of the area of the gate oxide
10
and of its thickness. As long as the area of polysilicon over the field oxides
14
is no larger than K times the area over the thin gate oxides
10
(where K varies according to the specific manufacturing process), the F-N tunneling will not occur. Alternatively, the total charge passing through the oxide will be small enough not to cause breakdown of the oxide. Chip designers are required to design their polysilicon elements accordingly, to minimize the amount of F-N tunneling by reducing the area of the field oxide relative to the area of the gate.
As long as the polysilicon etch is followed by a high temperature operation, the charge stored in the polysilicon due to the charging effect will be removed.
The polysilicon etch operation is not the only one which occurs in the presence of a plasma and which, accordingly, is affected by the charging effect. Etching also occurs when creating metal lines, via connections and pads and all processes involving the removal of photoresist and plasma-based cleaning.
For those processes which are not followed by high temperature processes, the charge accumulated therein is not removed. This is of particular concern for memory transistors which are designed to store charge and which, therefore, should not accumulate any charge until programmed to do so. Other sensitive devices, such as MOS transistors with thin gate oxides, must also be protected in other ways.
FIGS. 2A and 2B
, to which reference is now made, illustrate an exemplary memory transistor in cross-sectional and layout views, respectively. The memory transistor includes gate oxide
10
, polysilicon element
12
, a source junction
30
and a drain junction
32
. Junctions
30
and
32
are found on either side of polysilicon element
12
. Connected to polysilicon element
12
and to junctions
30
and
32
, via contacts
33
, are metal lines
34
. Protecting the remaining portions of polysilicon element
12
and the junctions
30
and
32
is an insulating layer
36
.
FIG. 2A
also shows photoresist elements
35
which are used to pattern the metal lines
34
. It is noted that, for clarity,
FIG. 2B
does not show photoresist elements
35
. Also, for clarity and simplicity,
FIG. 2B
does not show all the details typical to memory and MOS transistors (like floating gates, etc.).
As mentioned hereinabove, the etching processes used for metal lines
34
and the etching process of photoresist elements
35
occur in the presence of a plasma and can potentially induce charge into polysilicon element
12
. Like charge injected during programming, the induced charge causes F-N tunneling which results in breakdown of the gate oxide. This reduces the yield.
FIGS. 3A
,
3
B and
3
C, to which reference is now made, illustrate the solution in side cross-sectional, layout and circuit views, respectively. A metal line
40
, which is connected to the polysilicon element
12
, is laid down such that it is also connected, via a contact
42
, to an n+ area
44
which was previously embedded in the substrate
8
. Since substrate
8
is a p-element, there is a p-n junction at the intersection of area
44
with substrate
8
. In other words, metal line
40
is connected to a diode junction (the intersection of area
44
with substrate
8
).
FIG. 3C
shows the circuit of FIG.
3
A. The memory transistor to be protected, formed of gate oxide
10
and polysilicon element
12
, is labeled
46
, and the diode junction is shown as a diode
48
. The gate G of memory transistor
46
is connected to diode
48
via metal line
40
.
Whenever polysilicon element
12
collects charge during a plasma-based operation, metal line
40
will conduct the charge away from polysilicon element
12
and towards n+ area
44
. When the voltage drop between the polysilicon element
12
and the substrate
8
is high enough, diode junction
48
will breakdown, becoming a reverse-biased diode and causing charge to leak therethrough. This is known as “leakage current” and it pulls charge away from polysilicon element
12
. The leakage current limits the voltage drop between the polysilicon element
12
and the substrate
8
, typically to 7-9V, which is a low enough level to ensure no F-N tunneling.
If diode junction
48
is not fully covered by metal, it can become activated by the presence of light in the plasma. This produces a “photocurrent” which also pulls charge from polysilicon element
12
. This mechanism is difficult to accurately control.
Unfortunately, diode junction
48
is always present in the chip, even though it is not necessary for the normal functioning of the chip. In fact, if it is not turned off during the nominal operation of the chip, it limits the voltage that can be applied to the protected node, metal line
40
. Also, it drains an unwanted leakage current to ground, which might, in some applications be unacceptable. This diode cannot protect memory transistors since the latter are sensitive to lower voltages during plasma etching and the clamping voltage of the diode is too
Bloom Ilan
Eitan Boaz
Darby & Darby
Lee Calvin
Saifun Semicinductors Ltd.
Smith Matthew
LandOfFree
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