Method and circuit for matching sense amplifier trigger...

Details Method and circuit for matching sense amplifier trigger... Method and circuit for matching sense amplifier trigger...

2005-06-07

2005-06-07

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S205000, C365S207000, C365S208000

Reexamination Certificate

active

06903985

ABSTRACT:
A circuit for matching sense amplifier trigger signal timing to data bit line separation timing in a self-timed memory array includes: a source of a self-timed word line signal for a self-timed memory array; a transmission gate coupled to the source of the self-timed word line signal for propagating a timing delay and a ramp rate of the self-timed word line signal in response to a corresponding self-timed word line enable signal; and a selectable number of one or more self-timed pull-down core cells for summing a self-timed bit line drive current of each of the selectable number of one or more self-timed pull-down core cells to generate a sense amplifier trigger signal.

REFERENCES:
patent: 4421996 (1983-12-01), Chuang et al.
patent: 5053998 (1991-10-01), Kannan et al.

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