Method and circuit for logic output buffer

Details Method and circuit for logic output buffer Method and circuit for logic output buffer

1998-12-02

2003-07-22

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S086000, C326S087000, C326S017000, C326S119000, C326S121000, C327S170000

Reexamination Certificate

active

06597199

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to a digital logic circuit, and more particularly to a logic output buffer and related circuitry.
Digital logic circuits are used for various electronic applications such as microprocessors, controllers, digital signal processors, memory devices, and so on. Digital logic circuits can be classified into three popular logic families: (1) transistor-transistor logic (TTL), (2) emitter-coupled logic (ECL), and complementary metal-oxide-semiconductor (CMOS). Because of their low dissipation power, compact design, and noise immunity, CMOS logic circuits offer advantages over circuits of other logic families.
For a digital logic circuit, each output signal is typically driven by a logic output buffer. The output buffer is designed to provide greater drive capability than that of the internal circuits. This additional drive capability is required because of the load capacitance and impedance associated with each output line. Generally, higher output current is required to drive more load capacitance.
The drive capability of the output buffer is measured by its slew rate, or its ability to quickly charge or discharge an output line. Faster slew rate can be obtained by increasing the switching speed of the output buffer and also by providing the output buffer with greater drive current. However, both of these characteristics also result in greater switching noise during signal transitions. A circuit designer facing these conflicting design requirements must compromise between enhancing drive capability and reducing switching noise.
FIG. 1
is a simplified schematic of a conventional non-inverting CMOS output buffer
100
. Output buffer
100
includes an inverting buffer
110
and two output transistors, a P-channel transistor
112
and an N-channel transistor
114
, coupled in series. Transistors
112
and
114
are metal-oxide-semiconductor (MOS) enhancement mode devices. The input signal (vin) couples to the input of a buffer
110
. The output of buffer
110
couples to the gates of transistors
112
and
114
. The source of P-channel transistor
112
couples to an upper power supply (VDD) and the source of N-channel transistor
114
couples to a lower power supply (VSS). The drains of both transistors
112
and
114
couple together and form the output of buffer
100
.
Usually, by selecting the proper betas for the output transistors and the ratio of the transistor betas, a circuit designer can obtain certain circuit characteristics. The betas, in turn, can be controlled by properly sizing the transistors. For a conventional output buffer, the degree of control is limited and a sub-optimal circuit design is typically produced.
SUMMARY OF THE INVENTION
The invention provides a logic output buffer having one or more of the following advantages: (1) faster slew rate, (2) reduced switching noise during signal transitions, (3) improved switching time, and others advantages. The output buffer includes a pair of output transistors. At least one of the output transistors is designed with dynamically adjustable beta that allows for robust control of the output buffer operating characteristics. The beta can be adjusted by changing the size of the output transistor. The transistor size can be changed by enabling and disabling additional output transistor(s).
In a specific embodiment, the output buffer includes a pair of MOS output transistors, a P-channel transistor and an N-channel transistor, coupled in series and to respective supply sources. An additional P-channel output transistor is coupled in series with a control transistor, the combination of which is coupled in parallel with the P-channel output transistor. The additional output transistor is selectively enabled, through the control transistor, prior to rising transitions at the output of the buffer. The additional output transistor provides at least some of the advantages described above.
In another specific embodiment, the output buffer includes a pair of MOS output transistors coupled as in the above embodiment. An additional N-channel output transistor is coupled in series with a control transistor, the combination of which is coupled in parallel with the N-channel output transistor. The additional output transistor is selectively enabled to provide at least some of the aforementioned advantages.
In yet another specific embodiment, the output buffer includes a pair of MOS output transistors coupled as in the above embodiment. Two additional output transistors, one P-channel and one N-channel, are provided. Each additional output transistor couples in series with a control transistor, the combination of which is coupled in parallel with the similar channel type output transistor. The additional output transistors are selectively enabled to provide at least some of the aforementioned advantages.
A control circuit is used to generate the control signal to enable and disable the additional output transistor(s). The control circuit can be designed to accept either the input signal (Vin) or the output signal (Vout) of the output buffer to which the control circuit couples.
Additional embodiments can be designed using the inventive concept described herein. For example, one or more “enable” transistors can be provided to activate and deactivate the output buffer.


REFERENCES:
patent: 5594361 (1997-01-01), Campbell
patent: 5604453 (1997-02-01), Pedersen
patent: 5672983 (1997-09-01), Yamamoto et al.
patent: 5760620 (1998-06-01), Doluca
patent: 5949259 (1999-09-01), Garcia

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