Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2006-10-17
2006-10-17
Choi, Woo H. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S118000
Reexamination Certificate
active
07124240
ABSTRACT:
An SDRAM and method for operating it provide for increased data access speed. The SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A plurality of primary sense amplifier sets are provided, each set being associated with a respective pair of the memory blocks and located adjacent thereto. A row cache is provided in the central memory region, and row decoders decode a row address in response to a “bank activate” command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, prior to application of a “read” command to the SDRAM. Column decoders decode a column address in response to a “read” command and for reading data from the cache in accordance with the decoded column address.
REFERENCES:
patent: 5025421 (1991-06-01), Cho
patent: 5226009 (1993-07-01), Arimoto
patent: 5301162 (1994-04-01), Shimizu
patent: 5421000 (1995-05-01), Fortino et al.
patent: 5528552 (1996-06-01), Kamisaki
patent: 5680363 (1997-10-01), Dosaka et al.
patent: 5692148 (1997-11-01), Kundu
patent: 5706244 (1998-01-01), Shimizu
patent: 5721862 (1998-02-01), Sartore et al.
patent: 5748914 (1998-05-01), Barth et al.
patent: 5881009 (1999-03-01), Tomita
patent: 5887272 (1999-03-01), Sartore et al.
patent: 5900011 (1999-05-01), Saulsbury et al.
patent: 5950220 (1999-09-01), Quach
patent: 6295593 (2001-09-01), Hsu et al.
patent: 6526471 (2003-02-01), Shimomura et al.
patent: 6546453 (2003-04-01), Kessler et al.
patent: 2002/0003741 (2002-01-01), Maesako et al.
Dosaka, K. et al.; “A 100-MHz 4-Mb Cache DRAM with Fast Copy-Back Scheme”;IEEE Journal of Solid-State Circuits; Nov. 1992.
Enhanced Memory Systems, Inc.; “Preliminary Data Sheet,—64Mbit—Enhanced SDRAM, 8Mx8, 4Mx16 ESDRAM”; pp. 1-33; 2000 Enhanced Memory Systems, 1850 Ramtron Drive, Colorado Springs, Colorado, (800) 545-DRAM, http://www.edram.com.
Choi Woo H.
Purple Mountain Server LLC
Townsend and Townsend / and Crew LLP
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