Method and circuit for increased noise immunity for clocking...

Details Method and circuit for increased noise immunity for clocking... Method and circuit for increased noise immunity for clocking...

2006-04-25

2006-04-25

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S021000, C326S026000, C326S027000, C327S108000

Reexamination Certificate

active

07034566

ABSTRACT:
Aspects for increased noise immunity for clocking signals in high speed digital systems are described. The aspects include buffering a differential clock signal with a single buffer circuit for a plurality of load circuits and configuring the single buffer circuit to adjust to alterations in the number of load circuits receiving the differential clock signal. The configuring achieves a constant bandwidth and voltage level for the clock signal output while adjusting to alterations in the number of load circuits.

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