Method and circuit for implementing enhanced eFuse sense...

Details Method and circuit for implementing enhanced eFuse sense... Method and circuit for implementing enhanced eFuse sense...

2008-02-11

2010-06-01

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S225700, C365S189090, C365S189110

Reexamination Certificate

active

07729188

ABSTRACT:
A method and circuit for implementing an eFuse sense amplifier, and a design structure on which the subject circuit resides are provided. A sensing circuit includes a pair of cross-coupled inverters, each formed by a pair of series connected P-channel field effect transistors (PFETs) and an N-channel field effect transistor (NFET). A first pull-up resistor is coupled between a positive voltage supply rail and a first sensing node of the sensing circuit. A second pull-up resistor is coupled between a positive voltage supply rail and a second sensing node of the sensing circuit. A first bitline is coupled to the first sensing node of the sensing circuit and a second bitline coupled to the second sensing node of the sensing circuit. One of a respective reference resistor and a respective eFuse cell is selectively coupled to the first bitline and the second bitline.

REFERENCES:
patent: 6956781 (2005-10-01), Oyama
U.S. Appl. No. 11/622,519, filed Jan. 12, 2007 by Anthony Gus Aipperspach et al., entitled Method and Apparatus for Implementing eFuse Sense Amplifier Testing Without Blowing the eFuse.

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