Method and circuit for implementing digital delay lines...

Details Method and circuit for implementing digital delay lines... Method and circuit for implementing digital delay lines...

1998-11-13

2001-08-14

Gossage, Glenn (Department: 2759)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S167000, C711S137000, C365S194000, C084S604000

Reexamination Certificate

active

06275899

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to digital signal processing, and more particularly to method and circuit for implementing digital delay lines that can be used, for example, for audio applications.
Delay lines are commonly used in the electronics art to provide predetermined amounts of delay for signals. The delay facilitates the implementation of many functions and features. For example, in the field of audio signal processing, digital audio delay lines are used to provide echo effects, reverberation effects, distortion effects, three-dimensional (3-D) audio, and environmental modeling.
A digital delay line is conventionally implemented with a block of memory that is accessed using two pointers, a read pointer and a write pointer. The memory block contains data samples. The read and write pointers point to the locations in the delay line containing the current read and write samples, respectively. As a data sample is written to the current location in the delay line, the write pointer is advanced to the next location. Similarly, as a data sample is retrieved from the delay line, the read pointer is advanced to the next data sample. The difference between the read and write pointers represents the signal delay, in sample periods. By adjusting the location of either the read or write pointer, or both, different amounts of delay (albeit in discrete steps) can be obtained.
Many digital signal processing (DSP) algorithms that use digital delay lines require access to the delay lines with minimal latency (or low or near-zero access delay). Typically, a relatively large number of delay lines is needed to support these algorithms. Further, a read and a write access is typically performed for each delay line and for each sample period. These factors necessitate the use of a memory having high bandwidth and low access latency.
To satisfy these memory requirements, one conventional technique utilizes a local memory to implement the delay lines. Each delay line is accessed with individual read and write operations that are separate from those of other delay lines. The local memory is typically directly coupled to a digital signal processor that executes the DSP algorithm. The direct coupling of these circuit elements allows the processor to access the local memory with low latency, on-demand (i.e., as needed by the processor), and on a sample-by-sample basis.
However, as the requirement for local memory increases in size, it becomes less cost effective to use local memory to implement these delay lines. Also, in today's computing environment, commonly used memory devices have high capacity and are relatively inexpensive. Unfortunately, these memory devices are typically coupled to a bus that has high latency. Further, for improved efficiency, the bus typically transfers a block of data at a time. The high latency of the bus, the access latency of the memory device, and the tendency of both to operate in “burst” mode are contrary to the requirements of the DSP algorithms for low-latency, on-demand access to individual samples.
One conventional technique attempts to resolve these disparities by performing a read request of a data sample one sample period in advance of when the data sample is needed and a write request after a write data sample is calculated. These read and write requests are performed as individual (and independent) operations and are, therefore, inefficient. Further, these requests operate on single data sample and, consequently, the design can tolerate only one sample period of latency without producing artifacts (i.e., audible defects). Thus, this technique is only marginally effective at addressing the high-latency and burst characteristics of the bus.
Another conventional technique partially resolves these disparities by employing a small temporary memory. In this technique, a block of data samples from a main memory is provided to the temporary memory during a read operation. When the digital signal processor requests a data sample, the address associated with that data sample is compared with the addresses of the data samples contained in the temporary memory. If the requested data sample resides in the temporary memory, it is returned to the digital signal processor. Otherwise, a request is made to transfer the next block of data samples from main memory to the temporary memory. The improvement provided by the temporary memory alleviates some problems, but this technique is still inefficient (and sometimes ineffective) because of the need to wait for a data transfer across a high latency bus when the requested data sample is not currently available in the temporary memory.
Thus, methods and circuits that efficiently implement digital delay lines, particularly for audio applications, are much needed in the art.
SUMMARY OF THE INVENTION
The invention provides techniques for implementing digital delay lines that are used for various applications, including audio signal processing. A specific embodiment of the invention provides a delay line circuit that includes a main memory, a cache memory, and a signal processor. The cache memory operably couples to the main memory, and the signal processor operably couples to the cache memory.
The main memory implements one or more digital delay lines, as many delay lines as required by a digital signal processing (DSP) program running on the signal processor, up to a predetermined number. The delay lines hold data samples to be operated on, or produced by, the DSP program. Each delay line has a read pointer and a write pointer, with the difference between the read and write pointers corresponding to the amount of delay, in sample periods. The delay lines can be efficiently implemented as circular buffers.
The cache memory implements a number of delay caches that temporarily store data samples and support the delay lines. In one implementation, each delay line is associated with a read cache and a write cache. A block of data samples is “pre-fetched” from a delay line in the main memory and provided to the associated read cache. The data samples in the read cache are then accessed, as needed, by the signal processor. Data samples generated by the DSP program are provided to the write cache. Periodically, a block of data samples is “post-written” from the write cache to its corresponding delay line in the main memory.
Each active delay cache is selected for servicing once every servicing period. Servicing entails performing a data transfer operation between the delay cache and its corresponding delay line. The servicing period is selected based, in part, on the cache size and the number of delay caches. The servicing is further designed such that the read caches do not underflow (i.e., become empty) and the write caches do not overflow (i.e., become full). This design effectively “anticipates” data accesses by the signal processor.
The delay caches can be selected for servicing by the use of a round-robin scheme, a priority scheme, or some other schemes. Further, for some bus implementations, the starting address of the delay line for each data transfer operation is adjusted to more fully utilize the capacity of the bus, as will be explained in greater detail below.
The invention effectively allows the signal processor to have low latency access to individual data samples while experiencing minimal effects from the high-latency, burst characteristics of the bus and main memory.
The foregoing, together with other aspects of this invention, will become more apparent when referring to the following specification, claims, and accompanying drawings.


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