Image analysis – Histogram processing
Reexamination Certificate
1998-02-20
2001-04-17
Couso, Yon J. (Department: 2723)
Image analysis
Histogram processing
C348S672000, C358S522000
Reexamination Certificate
active
06219447
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and circuit for extracting a histogram and a cumulative distribution function (CDF) for an image enhancement apparatus. More particularly, the present invention relates to a simple extraction circuit having an integrated structure, which controls the extraction periods for a histogram and a CDF using a memory, and a method therefor.
2. Description of Related Art
Histogram equalization involves converting a given input image on the basis of the histogram of the input image. Here, the histogram is a distribution of gray levels in a given input image. The histogram of the gray levels provides an entire representation of the appearance of an image. Appropriately adjusting the gray levels according to the sample distribution of an image enhances the appearance or the contrast of the image.
Histogram equalization, as a method for enhancing the contrast of a given image according to a sample distribution of the image, has been the most widely known among many methods for contrast enhancement, and is disclosed in the following documents: [1] J. S. Lim, “Two-Dimensional Signal and Image Processing”, Prentice Hall, Eaglewood Cliffs, N.J. 1990; and [2] Reading, Mass. 1977.
Such a technique using the histogram of a given image has been usefully applied to various fields such as medical image processing, infrared image processing, radar image processing, etc.
Meanwhile, a conventional image enhancement apparatus adopting a histogram equalizer to improve the contrast of an image is shown in FIG.
1
. Since the conventional image enhancement apparatus has been disclosed in U.S. Pat. No. 5,388,168 issued to Hirohiko Sakashita. et al, on Feb. 7, 1995, it will be described only briefly here.
Referring to
FIG. 1
, a cumulative histogram circuit
10
receives a digital input luminance signal Y and obtains cumulative histograms M
64
, M
128
and M
192
. A latch circuit
20
temporarily stores the histograms M
64
, M
128
and M
192
obtained by the cumulative histogram circuit
10
. The obtained histograms are kept until the cumulative histogram circuit
10
obtains the subsequent histograms and outputs the result thereof. An interpolation circuit
30
interpolates a new input luminance signal Y in real time, on the basis of the cumulative histograms M
64
, M
128
and M
192
previously obtained by the cumulative histogram circuit
10
, to correct the new input luminance signal, and then outputs the resultant signal.
FIG. 2
is a block diagram of the cumulative histogram circuit
10
shown in FIG.
1
. Referring to
FIG. 2
, the conventional cumulative histogram circuit
10
has an integrated structure where histogram and cumulative distribution function (CDF) are extracted together. That is, the conventional cumulative histogram circuit
10
includes comparators
11
,
12
and
13
for comparing the input luminance signal Y with reference levels
64
,
128
and
192
, and counters
14
to
16
which count according to the outputs of the comparators
11
,
12
and
13
, respectively, and are reset by a clear signal CLR.
The first comparator
11
compares the input luminance signal Y with the first reference level
64
, and the first counter
14
is incremented when the input luminance signal value is less than the first reference level
64
. The second comparator
12
compares the input luminance signal Y with the second reference level
128
, and the second counter
15
is incremented when the input luminance signal value is less than the second reference level
128
. The third comparator
13
compares the input luminance signal Y with the third reference level
192
, and the third counter
16
is incremented when the input luminance signal value is less than the third reference level
192
. Assuming that the value of the input luminance signal Y is 100, the second and third comparators
12
and
13
each output logic high. Thus, the second and third counters
15
and
16
each increase their count values by one. Supposing that the value of the input luminance signal Y is 32, the first to third comparators
11
to
13
all output logic high, and the first to third counters
14
to
16
all increase their count values by one. The distribution of gray levels of an input image is extracted through the above process.
For convenience of explanation, the cumulative histogram circuit
10
shown in
FIG. 2
has an 8-bit input digital encoded luminance signal having a value ranging from 0 to 255, and requires only three counters and comparators by setting three comparative levels of
64
,
128
and
192
. However, in practice, the cumulative histogram circuit
10
must have more comparative levels. For example, if the number of comparative levels is set to be 32, e.g., 8, 16, 24, 32, 40, . . . , 240 and 248, then the numbers of comparators and counters must also be increased to 32. Therefore, the size of the required hardware increases. Also, since the input luminance signal is input concurrently to the plurality of comparators whose number corresponds to the number of comparative levels, problems such as a fan-in phenomenon may occur. Furthermore, when the input luminance signal has a very small value, all of the comparators are enabled so that the counters and all of the comparators operate simultaneously. As a result, power consumption is increased due to the many counting operations. Further, the number of comparators and counters which operate depending on the level of the input luminance signal are limited, thereby making power consumption irregular.
SUMMARY OF THE INVENTION
To solve the above problem, it is an object of the present invention to provide a method for extracting a histogram and a cumulative distribution function (CDF) by controlling the extraction periods for the histogram and CDF using a memory.
It is another object of the present invention to provide a circuit for extracting a histogram and a CDF which has an integrated structure and is constituted of simple hardware, by extracting the histogram and the CDF in different periods using a memory.
To accomplish the first object, there is provided a histogram/CDF extracting method for enhancing the quality of an image by histogram-equalizing an image signal expressed according to a predetermined number of gray levels. The method comprises the steps of inputting an input digital image signal as an address; increasing the value of data stored at the input address; obtaining a histogram indicating the number of samples distributed to each gray level by repeating the address input step and the data value increasing step for a first predetermined period of time; and obtaining a cumulative distribution function (CDF) value of each gray level by cumulatively integrating the numbers of samples from the lowest gray level for a second predetermined period of time on the basis of the obtained histogram value.
To accomplish the second object, there is provided a histogram/CDF extracting circuit in an image enhancement apparatus including a histogram/CDF extracting circuit for extracting a histogram indicating the number of samples distributed to each gray level of an input digital image signal and calculating a CDF value of each gray level on the basis of the extracted histogram, and a look-up table (LUT) for storing an enhanced signal obtained by multiplying a maximum gray level value by the CDF value of each input gray level extracted from the histogram/CDF extracting circuit, and reading out a corresponding enhanced signal according to the levels of the input image signal. The histogram/CDF extracting circuit comprises a first selector for selecting a digital image signal in a histogram extraction mode and selecting an incrementing address in a CDF extraction mode; a memory for receiving a signal selected by the first selector as an address, and writing a histogram value increased by “1” to the address, in the histogram extraction mode, and a current input CDF value thereto in the CDF extraction mode; a first buffer for temporarily
Couso Yon J.
Samsung Electronics Co,. Ltd.
Sughrue Mion Zinn Macpeak & Seas, PLLC
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