Method and circuit for enabling a clock-synchronized read-modify

Details Method and circuit for enabling a clock-synchronized read-modify Method and circuit for enabling a clock-synchronized read-modify

1997-08-04

1999-11-30

Peikari, B. James

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

36518904, 36523006, G06F 1206

Patent

active

059960523

ABSTRACT:
A semiconductor memory enabling a read modify write operation of data, comprising: a memory cell array including a plurality of memory cells arranged in a matrix and able to be written with and read out data; a read address decoding means for independently decoding an address of a read memory cell in response to a read address; a write address decoding means for independently decoding an address of a write memory cell in response to a write address; a data reading means for reading data of a memory cell addressed by the read address decoding means; a data writing means for writing data to a memory cell addressed by the write address decoding means; and an address delay means by which a write address decoded by the write address decoding means is delayed by a predetermined time from a read address decoded by the read address decoding means, wherein the predetermined time is set as a predetermined plurality of times of basic synchronization pulse periods so that the data read modify write operation is accomplished in a pipeline manner by the basic synchronized pulse.

REFERENCES:
patent: 5001665 (1991-03-01), Gergen et al.
patent: 5023838 (1991-06-01), Herbert
patent: 5297071 (1994-03-01), Sugino
patent: 5802586 (1998-09-01), Jones et al.

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