Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2006-05-09
2006-05-09
Le, Thong Q. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Signals
C365S230060, C365S207000
Reexamination Certificate
active
07042776
ABSTRACT:
A method and circuit for adjusting the read margin of a self-timed memory array. The electronic circuit, including: a memory cell array including a sense amplifier self-timed decode circuit adapted to set a base read time delay of the memory cell array; and a read delay adjustment circuit coupled to the memory cell array, the read delay adjustment circuit adapted to adjust the base read time delay of the memory array based on an operating frequency of the memory cell array.
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Canada Miles G.
Geissler Stephen F.
Houle Robert M.
Lee Dong-ho
Ramadurai Vinod
International Business Machines - Corporation
Le Thong Q.
LeStrange Michael
Schmeiser Olsen & Watts
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