Patent
1993-04-06
1996-04-23
Robertson, David L.
395445, G06F 1100
Patent
active
055111807
ABSTRACT:
Disclosed are a circuit and method for dynamically determining cache memory size. The method comprises the steps of (1) writing a replacement data pattern into a first addressable location of a cacheable portion of addressable space, thereby placing the replacement data pattern into a corresponding first addressable location in a cache memory and setting a tag in the first addressable location, (2) accessing an assumed number of remaining addressable locations in the portion of the addressable space thereby setting tags in each of the remaining addressable locations and (3) reading the first addressable location in the cache memory to determine whether the replacement data pattern remains in the first addressable location, the cache memory being of an assumed size if the replacement data pattern is not in the first addressable location in the cache memory. The circuit and method are able to size cache memory without reference to cache size data stored in cache controllers or hardware timers.
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patent: 5175836 (1992-12-01), Morgan
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patent: 5287481 (1994-02-01), Lin
Dell USA L.P.
Garrana Henry
Kahler Mark
O'Neill David J.
Robertson David L.
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