Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-03-12
2001-12-11
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S018000, C703S016000, C702S060000, C702S120000, C714S030000, C713S340000
Reexamination Certificate
active
06330703
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor logic circuit, for example, a microprocessor or a RAM having a plurality of flip-flops and logic gate circuits. More specifically, the present invention relates to controlling a logical operation, controlling the power consumption of the semiconductor logic circuit arbitrarily, measuring a value of power consumption, and calculating in advance the power consumption when designing the semiconductor logic circuit.
2. Description of the Related Art
In order to activate a semiconductor logic circuit, such as a microprocessor, power supply lines and signal lines of the semiconductor logic circuit are wired to a package, such as a programmable gate array (PGA), potting, mounting them on the printed circuit board, and connecting the printed circuit board to the power supply unit (such as an electric cell). In order for the logic circuit to operate normally, it is necessary to determine the number of wiring lines for the power supply, the width of each power supply wiring line, a value of the resistance, the inductance and the capacitance of wiring for the power supplied to both the package and the circuit board, and further to set a total amount of current supply from the power supply unit to an optimal value. To achieve this purpose, it is important to predict the power consumption accurately when activating the semiconductor logic circuit.
As indicated in Japanese patent No. 5-265605, for example, the method of employing a hand calculation or a logic simulator is used so as to predict the power consumption of the semiconductor logic circuit for designing.
FIG. 11
is a flow chart for designing a semiconductor logic circuit and producing a semiconductor chip according to the prior art. For designing the logic of the semiconductor circuit, logical design data
1103
having a circuit diagram of the semiconductor logic circuit shown in
FIG. 12
, for example, is generated by executing a logic design subroutine
1102
based upon a functional specification
1101
, which defines function, operational frequency and allowable power consumption of the semiconductor logic circuit being designed. The power consumption data
1105
, having a power consumption timing chart as shown in
FIG. 13
, is generated when each logic gate circuit consumes its power for switching its output, based upon the semiconductor device data
1104
used for the semiconductor logic circuit. An average data for the rate of operation
1107
for each logic gate circuit of the semiconductor logic circuit, which has a timing chart for the rate of operation as in
FIG. 13
, is generated based upon the analysis of the operation for several kinds of the predetermined programs
1106
executed in the semiconductor logic circuit. The confirmation of function
1108
and the power consumption calculation
1109
are executed by hand calculation or by a calculation program, based upon the logical design data
1103
, the power consumption data
1105
, and the average data for the rate of operation
1107
. If the results at the steps
1108
and
1109
do not satisfy the function and the power consumption defined in the step of the functional specification
1101
(i.e., the result is NG
1
), the logical design data
1103
is corrected by feeding-back the results and re-executing the logic design subroutine
1102
. This feedback routine repeats itself until the above results of steps
1108
and
1109
satisfy the function and the power consumption defined in the step
1101
(i.e., the result is OK
1
).
In designing the layout of the semiconductor circuit, the physical design data
1111
is produced by executing the layout design subroutine
1110
, based upon the logical design data
1103
. The test program
1112
used for an operation test of the semiconductor logic circuit is produced by pulling a representative operation program from several kinds of predetermined programs
1106
executed in the semiconductor logic circuit. The detailed functional test
1113
and the detailed calculation of the power consumption
1114
are executed by using the logical simulation program, based upon the physical design data
1111
, the semiconductor device data
1104
, and the test program data
1112
. If the results at steps
1113
and
1114
do not satisfy the function and the power consumption defined in the step of the functional specification
1101
(i.e., the result is NG
2
), either the logical design data
1103
is corrected by feeding-back the results and re-executing the logic design subroutine
1102
or the physical design data
1111
is corrected by re-executing the layout design subroutine
1110
. This feedback routine repeats itself until the results of steps
1113
and
1114
satisfy the function and the power consumption defined in step
1101
(i.e., the result is OK
2
).
The prototype semiconductor chip is produced according to the physical design data
1111
at step
1115
. Both the functional operation test
1117
and the measurement of the power consumption
1118
are executed by running the test program
1112
on the semiconductor logic circuit
1116
produced at step
1115
. If the results at the steps
1117
and
1118
do not satisfy the function and the power consumption defined in the functional specification
1101
(i.e., the result is NG
3
), either the chip is reproduced at step
1115
or the logical design data
1103
is corrected by feeding-back the results and re-executing the logic design subroutine
1102
, or the physical design data
1111
is corrected by re-executing the layout design subroutine
1110
. If the results at steps
1117
and
1118
satisfy the function and the power consumption defined in step
1101
(i.e., the result is OK
3
), the chip produced at step
1115
is determined as a good quality semiconductor logic circuit at step
1119
.
SUMMARY OF THE INVENTION
The present invention overcomes the deficiencies in the prior art. The prior art flow chart of
FIG. 11
is not sufficient to design a chip to handle power consumption when the rate of operation for the logic circuit varies extremely during a short period of time. This is because the semiconductor chip is designed by calculating the power consumption of the semiconductor logic circuit based upon an assumed average rate of operation obtained from the predetermined programs
1106
.
If an actual program is executed in the semiconductor logic circuit, the rate of operation might vary frequently. Therefore, for the detailed calculation of the power consumption
1114
at the process of designing the layout and/or for the measurement of the power consumption
1118
at the process of producing a prototype semiconductor chip, the test program
1112
considering the variation is required to be used in the prior art flow chart of FIG.
11
. However, the more complicated the semiconductor, the harder it is to produce test program
1112
. It is impossible to generate test program
1112
assuming the most extreme condition that can occur and to execute the operation test
1117
.
Because of these disadvantages of the prior art as shown in
FIG. 11
, when several kinds of programs are executed, an unpredictable variation for the rate of operation occurs. As a result, the semiconductor logic circuit cannot supply sufficient power from the power supply source, causing operational failure, even if the power consumption of the semiconductor logic circuit satisfies the functional specification for the operation test.
FIG. 13
is an example timing chart showing the extreme variation of power consumption that occurred, with respect to such unpredictable variation for the rate of operation if the combined circuit group is a dynamic circuit having the control signal applied. Further, the example circuit diagram of a general semiconductor logic circuit retrieved from the logical design data
1103
in the prior art flow chart of
FIG. 11
to perform a logical operation and to result in the extreme variation of the power consumption as mentioned above is introduced in FIG.
Chiba Tsuneyo
Saito Tatsuya
Yagyu Masayoshi
Yamamoto Masakazu
Yamashita Hiroki
Hitachi , Ltd.
Kik Phallaka
Mattingly Stanger & Malur, P.C.
Smith Matthew
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