Method and circuit for delayed branch control and method and cir

Details Method and circuit for delayed branch control and method and cir Method and circuit for delayed branch control and method and cir

1997-05-29

1999-11-30

Treat, William M.

Electrical computers and digital processing systems: processing

Processing control

Branching

G06F 938

Patent

active

059960698

ABSTRACT:
In a processor employing a delayed branch method, delayed branch control which does not complicate instruction execution sequence and improves the readability of a program on the assembler level is implemented without providing a control bit in an instruction code. The delayed branch control according to the present invention involves the use of a branch-information storing circuit for storing the occurrence or nonoccurrence of a branch in a specified one of a continuous sequence of cycles immediately before a current execute cycle which are equal in number to delay slots in the processor. In executing a delayed branch instruction, when the branch-information storing circuit stores the occurrence of a branch in the specified cycle, a branch is disabled. This prevents instruction execution sequence from being complicated even when individual branch conditions for consecutive delayed branch instructions are satisfied, so that the program on the assembler level is improved in readability. The branch-information storing circuit can simply be composed of a combination of a shift register, a counter, and a latch.

REFERENCES:
patent: 5471593 (1995-11-01), Branigin
patent: 5509130 (1996-04-01), Trauben et al.
patent: 5655097 (1997-08-01), Witt et al.
patent: 5706459 (1998-01-01), Atsushi
patent: 5706490 (1998-01-01), Beard et al.
patent: 5784603 (1998-07-01), Leung et al.
Patent Abstracts of Japan, vol. 11, No. 378 (P-645), Dec. 10, 1987 and JP 62-147530 A (Hitachi Ltd.) Jul. 1, 1987.
J. Cortadella et al: "Designing a Branch Target Buffer for Executing Branches with Zero Time Cost in a Risc Processor" Microprocessing & Microprogramming, vol. 24, No. 1-5, Aug. 1988, pp. 573-580, XP000038090.
A.M. Gonzalez: "A survey of branch techniques in pipelined processors" Microporcessing & Microprogramming, vol. 36, No. 5, Oct. 1993, pp. 243-257, XP000397907.
M. J. Mahon et al: "Hewlett-Packard Precision Architecture: The Processor" Hewlett-Packard Journal, vol. 37, No. 8, Aug. 1986, pp. 4-21, XP000211314.
G.B. Steven, et al., "ALU design and processor branch architecture" Microprocessing and Microprogramming, vol. 36, No. 5, Oct. 1993, Amsterdam, NL, pp. 259-278.
J.A. Derosa, et al., "An Evaluation of Branch Architectures" Proceedings of the 14.sup.th Annual International Symposium O Computer Architecture, Jun. 2-5, 1987, Pittsburgh, PA, US, pp. 10-16.

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