Method and circuit for controlling a first-in-first-out...

Details Method and circuit for controlling a first-in-first-out... Method and circuit for controlling a first-in-first-out...

1999-01-19

2002-04-30

Lee, Thomas (Department: 2782)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S036000, C710S020000, C710S021000, C710S053000, C710S052000, C710S056000, C711S100000, C711S147000, C711S173000, C703S013000

Reexamination Certificate

active

06381659

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to controlling a first-in-first-out (FIFO) buffer and more precisely to a FIFO controller for buffering a plurality of disparate data blocks or entities flowing between asynchronous data processes in a manner preventing overlap or corruption of data.
BACKGROUND OF THE INVENTION
FIFO structures are well known for buffering data passing between two data handling processes which operate asynchronously with respect to each other. A FIFO memory is a structure wherein data words, objects, blocks, or entities are taken out of the structure in the order of receipt. A sender places data objects into the FIFO structure, while a receiver collects the objects from the structure.
Referring to
FIG. 1
, generally, a first-in-first-out (FIFO) buffer
44
is used to provide temporary storage for data that is being transferred between two or more asynchronous data processing systems. These data processing systems typically have specialized clocking circuits, e.g. Clk-
1
and Clk-
2
operating at predetermined frequencies (phases) which are asynchronous with respect to each other. The FIFO buffer
44
shown in the
FIG. 1
example is, for example, a dual port memory array having a preferred row dimension of thirty two bits wide with thirty two rows in height or depth (i.e. a 32 by 32 memory array).
One typical data processing system is a disk-type magnetic recording system or disk drive
30
. The disk drive
30
uses a magnetic transducer element, or head
31
to record information onto (i.e., write) and to retrieve information from (i.e., read) a magnetic medium formed on a surface of a rotating disk
32
. Each storage disk
32
comprises an annular substrate onto which is deposited a magnetic recording medium. Although
FIG. 1
shows a single head
31
and disk
32
, in practice multiple storage surfaces and heads are frequently employed. In the
FIG. 1
example the storage surface of disk
32
is divided into thousands of concentric, annular bands, or “tracks”
33
each having a predetermined radial extent. Each head
31
is supported in close proximity to an associated disk
32
surface by a head positioning assembly, or actuator
34
, that supports the head
31
near the disk
32
surface and moves it from one radial position to another, thereby permitting use of a single head
31
for reading and writing along each of the multiple concentric tracks
33
. The positioner assembly
34
for each head
31
or group of heads
31
includes an actuator arm
35
and an actuator motor
36
. The actuator motor
36
moves the actuator arm
35
to change the position of the head
31
with relation to the tracks
33
on the disk
32
. A disk drive
30
having a plurality of disks
32
stacked on a common spindle will typically employ a single actuator motor
36
to move a corresponding number of ganged-together actuator arms
35
and heads
31
in unison. A disk controller (not shown) controls operations of the disk spindle and the actuator motor
36
.
The disk drive
30
, further includes a disk channel
37
, such as a partial-response maximum-likelihood (PRML) synchronous sampling data detection channel, for encoding, detecting, decoding and controlling flow of data read from or written to the disk
32
at a data rate in accordance with a disk clock CLK-
1
. The disk clock CLK-
1
may remain fixed, or it may be varied as a function of radius of a particular data track
33
(since relative rotational velocity varies with track radius). The disk drive
30
typically transmits data back and forth between itself and a random-access-memory (RAM) buffer
25
. The RAM buffer
25
includes one or a plurality of electronic data storage integrated circuit memory chips for storing data therein. The RAM buffer
25
is coupled with a RAM Port
26
. The RAM Port
26
is coupled to the disk drive
30
via a disk-direct-memory-access (DDMA)
40
, which is defined within the disk drive
30
. The RAM Port
26
circuit is further connected to several other clients including: a RAM buffer manager
24
; a standard bus interface
28
, such as a Small-Computer-System Interface (SCSI), which connects to a host computer
22
and also may be connected as well as to several other clients (n). The RAM Port
26
circuit provides access arbitration among the clients seeking access to the RAM buffer
25
, including the DDMA
40
, host interface
28
and other clients (n) such as a disk drive controller.
The DDMA
40
generally includes a RAM Port Interface circuit
42
, a FIFO buffer
44
, and a disk interface circuit
45
. The RAM Port interface
42
communicates data as well as control information to the RAM buffer
25
via the RAM Port
26
and RAM buffer manager
24
. The FIFO buffer
44
is connected to the RAM Port Interface
42
circuit and acts as a temporary storage space for data that is in the process of being transferred to/from the disk drive
30
and the RAM
25
. The disk interface circuit
45
is connected to the disk channel
37
, via a bus
27
, as well as to the FIFO buffer
44
. The disk interface
45
operates to communicate data to/from the disk channel
37
and storage surface of disk
32
.
The DDMA
40
further includes a disk read/write process control
41
and a RAM read/write process control
43
. The disk read/write process control circuit
41
is connected to the disk interface
45
and is synchronous with CLK-
1
of the disk channel
37
. The RAM read/write process control circuit
43
is connected to the RAM Port interface
42
and is synchronous with a second clock CLK-
2
used to write data to and from the RAM buffer
25
. The disk and RAM read/write process control circuits
41
,
43
enable the RAM Port interface
42
and the Disk Drive interface
45
to either read data from or write data to the FIFO buffer
44
depending on the direction of data flow between the RAM buffer
25
and the disk drive
30
.
In a typical data transfer from the disk drive
30
to the RAM buffer
25
, a plurality of data blocks written in tracks
33
are sensed as magnetic flux transitions by the head
31
and recovered as binary data by the disk channel
37
. The recovered data is transmitted to the FIFO buffer
44
via the disk interface
45
. Prior to writing data to the FIFO buffer
44
, a write-pointer register
48
is preset to point to the first row of the FIFO
44
. Next, the disk read/write process control circuit
41
is enabled for writing data to the FIFO buffer
44
, and the RAM read/write process control circuit
43
is enabled for reading data from the FIFO buffer
44
. Thereafter, the disk interface
45
begins writing 32-bit data segments to the FIFO buffer
44
synchronously with clock CLK-
1
. Additionally, the write-pointer address register
48
is incremented as each data segment is written into the FIFO buffer
44
. Once the FIFO buffer
44
accumulates a predetermined number of data segments, a control signal is issued to the RAM Port Interface
42
indicating that the FIFO buffer
44
has data which needs to be read out.
At this point, the RAM Port Interface
42
arbitrates with the RAM Port
26
for direct access to the RAM buffer
25
via the RAM buffer manager
24
. When access is granted to the RAM buffer
25
, the RAM Port Interface
26
reads data out of the FIFO buffer
44
and transmits the data to the RAM buffer
25
via RAM buffer manager
24
. Prior to the RAM Port Interface
42
reading data out of the FIFO buffer
44
, a read-pointer address register
46
is preset to point to the beginning of data written into the FIFO buffer
44
, i.e. the first row in this example. Thereafter, the RAM Port Interface
42
begins reading data segments from the FIFO buffer
44
in synchronism with clock CLK-
2
. The read-pointer address register
46
is incremented as each data segment is read from the FIFO buffer
44
. Once the read-pointer address register
45
is incremented to point to a next buffer row, the present buffer row is free to be written with a next data segment of the data block being transferred.
Since the FIFO buffer
44
hold

Affiliated with

Also associated with

Rating

Method and circuit for controlling a first-in-first-out... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and circuit for controlling a first-in-first-out..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and circuit for controlling a first-in-first-out... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2908314