Method and circuit for adding operands of multiple size

Details Method and circuit for adding operands of multiple size Method and circuit for adding operands of multiple size

1998-04-08

2000-03-21

Ngo, Chuong Dinh

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708518, G06F 750

Patent

active

060413417

ABSTRACT:
A circuiting method is disclosed for adding operands of multiple size. This circuit and method employ an n bit adder having n first and second inputs. A first m bit operand is inputted into the m least significant first inputs of the adder, where n is greater than m. A second m bit operand is inputted into the m least significant circuit inputs of the adder. A first (n-m) bit operand is inputted into the (n-m) most significant first inputs of the adder. Each bit of the first (n-m) bit operand represents logical 0. A second (n-m) bit operand is inputted into the most significant (n-m) second inputs of the adder. Each bit of the second (n-m) bit operand represents a logical 1. The first and second m bit operands, the first and second (n-m) bit operands and a carry in bit provided to a carry input node of the adder, are all inputted in parallel. In response, the adder generates n carry bits and n bit output operand. The least significant m bits of the n bit output operand and the most significant carry bit of the n carry bits represent the result of adding the first and second m bit operands and the carry in bit.

REFERENCES:
patent: 5249148 (1993-09-01), Catherwood et al.
patent: 5511017 (1996-04-01), Cohen et al.

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