Method and circuit for a least recently used replacement mechani

Details Method and circuit for a least recently used replacement mechani Method and circuit for a least recently used replacement mechani

1996-12-24

1998-09-15

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711 3, 711118, 711128, 711154, G06F 1200, G06F 1300

Patent

active

058095284

ABSTRACT:
An architecture and method of implementing an invalid data handling least recently used replacement mechanism in a cache memory system is provided that includes a first register stack, a second register stack and stack control logic. The first register stack includes registers for holding entry address information. The stack control logic includes logic for inhibiting the placement of invalidated entry addresses into a Most Recently Used register in the first register stack and directs that such invalidated entry addresses be input into the second register. The stack control logic further directs that any new entry addresses be placed in the first register stack where invalidated entry addresses has resided. A counter keeps count of the number of invalidated entry addresses input into the second register stack and toggles a multiplexer at a Least Recently Used Entry output of the first register stack to select as its output, the output of the second register stack. In this manner, invalidated entry address are output from the cache through the second register stack while valid Least Recently Used entry addresses remain in the first register stack.

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