Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate
2002-04-02
2003-10-28
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including signal comparison
C365S149000, C365S203000, C365S205000
Reexamination Certificate
active
06639846
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention proposes a circuit configuration and a method for a memory, in particular for a DRAM, having a multiplicity of memory cells disposed in rows and columns.
It is known, in order to read and evaluate the cell information of a memory cell of a dynamic random access memory (DRAM) module upon the activation of a corresponding word line, to reverse the charge of one of the two bit lines (read line) of a read memory in accordance with the potential of the memory cell, while a second bit line is used as a reference line. The sense amplifier measures the voltage difference between the two bit lines, evaluates it and sets the read line either to 0 volts or to the potential of the supply voltage. In this case, the reference line is subjected to charge reversal to the inverse polarity.
What is disadvantageous about the method is that the read signal can be impaired by a parasitic coupling capacitance between the activated read line and the reference line, but also by coupling capacitances with respect to the adjacent lines, since the coupling voltage can increase or decrease the read signal. This can lead to incorrect evaluations particularly when operating the memory module for the worst-case data combinations on bit lines or the memory cells thereof, since the measured voltage difference—caused by the parasitic coupling capacitance—between two adjacent bit lines is dependent on the data topology and the line routing thereof on the semiconductor chip of the memory module.
It has previously been attempted to solve this problem by reducing the parasitic coupling capacitances through skillful line routing. By way of example, in the configuration of “twisted bit lines”, the two assigned bit lines are disposed as far as possible multiply alternately crossed, thereby resulting in smaller coupling capacitances which largely compensate for one another owing to their alternating polarities. The configuration has the disadvantage, however, that the many crossovers on the memory module require more chip area, which is undesirable for cost reasons. Added to this is the fact that the crossovers likewise result in asymmetries in the layout that require an increased outlay on testing in the fabrication of the memory module. Moreover, the innumerable node contacts give rise to increased yield risk, since each node contact can represent an additional potential defect source. Overall, this solution is regarded as extremely unsatisfactory for technical and economic reasons.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method and a circuit configuration for a memory for reducing parasitic coupling capacitances which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which the interference from parasitic coupling capacitances is reduced in conjunction with a simplified memory organization.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory circuit configuration. The memory contains word lines disposed in a column form, bit lines disposed in a row form, sense amplifiers, and a multiplicity of memory cells connected to and activated by the word lines. The bit lines connect the memory cells to the sense amplifiers. If a respective word line of the word lines is activated, at least one of the bit lines being a first bit line and being associated with a respective memory cell of the memory cells electrically connects the respective memory cell to a respective sense amplifier of the sense amplifiers for reading-out a datum. The sense amplifiers during the reading-out on the first bit line put an adjacent one of the bit lines being a second bit line adjacent to the first bit line actively at a predetermined potential.
The circuit configuration according to the invention and the method according to the invention have the advantage that the many crossovers of the bit lines can be dispensed with, so that not only is chip area saved in the layout, but the test method for the memory module is also simplified owing to the maintained symmetry. In this case, it is regarded as particularly advantageous that the undesirable parasitic coupling capacitances are likewise reduced, so that, in particular also in the event of unfavorable line routing, the read signal can be measured virtually uncorrupted by the sense amplifier. As a result, the error rate for the measurement of the read signal is reduced and the yield can be increased in fabrication.
It is regarded as particularly advantageous that the sense amplifier puts or keeps the potential of the second bit line at the potential of the precharge state. As a result, the adjacent inactive bit lines (reference bit lines) advantageously act as shielding with respect to the activated bit line, without the need to implement further measures for compensation of the parasitic coupling capacitance.
One favorable solution is also seen in the fact that the sense amplifier puts the first bit line actively at the precharge potential, while it reads out the second bit line. As a result, the greatest possible freedom of configuration is obtained in the configuration of the bit lines. Furthermore, the test method can be carried out in a simplified fashion in a manner that saves time and costs.
A further alternatively advantageous configuration for reducing the parasitic coupling capacitances of the bit lines consists in connecting in each case the first and third bit line or the second and fourth bit line to a respective sense amplifier.
It is likewise advantageous for the architecture of the memory module for in each two adjacent bit lines to be connected to a respective sense amplifier. As a result, each desired bit line can be set actively or passively to a predetermined potential in a simple manner. In particular, in this way it is possible to use bit lines from adjacent activation arrays that are inactivated at the instant of the evaluation of the read signal.
An alternative solution that is regarded as particularly favorable also relates to using sense amplifiers that can carry out an evaluation of the read signal without a reference bit line. This makes it possible to save further bit lines on the memory chip, so that the available area can be utilized even better.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for reading a datum from a memory cell of a memory array via a first bit line. The memory array has a plurality of bit lines disposed next to one another. The method includes the steps of activating a word line connected to the memory cell for connecting the first bit line to the memory cell, putting at least one second bit line disposed next to the first bit line at a defined voltage, and reading-out and evaluating a voltage impressed on the first bit line.
In accordance with an added mode of the invention, there is the step of setting the defined voltage to be a precharge voltage to which the second bit line is charged prior to the reading-out of the datum.
In accordance with a further mode of the invention, there is the step of putting the word line at a further defined voltage during the reading-out.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and a circuit configuration for a memory for reducing parasitic coupling capacitances, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
REFERENCES:
patent: 5555203 (1996-09-01), Shiratake et al.
patent: 5815451 (1998-09-01), Tsuchida
patent: 6181620 (2001-01-01), Agata et al.
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Nelms David
Stemer Werner H.
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