Method and circuit arrangement for monitoring the operation...

Details Method and circuit arrangement for monitoring the operation... Method and circuit arrangement for monitoring the operation...

2006-07-18

2006-07-18

Le, Dieu-Minh (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S055000

Reexamination Certificate

active

07080281

ABSTRACT:
A counter (2) alters its counter variable (C) on the basis of a clock signal which is generated by an oscillator (3). If the reset signal (CT1) intermittently transmitted by the processor (1) during normal operation is absent, the count variable (C) reaches a first limit value (Cgr1). The counter (2) then sends an interrupt signal (IR) to the processor (1). If the reset signal (CT) continues to be absent and the count variable (C) reaches a second limit value (Cgr2), the counter (2) transmits a hardware reset signal (HWR) to the processor (1). This signal or the result of this signal (HWR) is also used to reset the counter (2), i.e. the count variable (C) is set to a predetermined start value (CSTART). Thus, in the absence of the reset signal (CT1) from the processor (1), an interrupt (IR) and a hardware reset signal (HWR) are cyclically transmitted.

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MCI4060B 14-Bit Binary Counter and Oscillator; Motorola, Inc., 1995.

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