Method and circuit arrangement for controlling write access...

Details Method and circuit arrangement for controlling write access... Method and circuit arrangement for controlling write access...

2007-05-29

2007-05-29

Auduong, Gene N (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100, C365S230060

Reexamination Certificate

active

11117698

ABSTRACT:
The invention relates to a method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets are written to the semiconductor memory per data burst, in which write access is initiated by a write command and the data packets which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal, where the data packets are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal, and where the data strobe write clock control signal has a defined state at the start of the write operation. The invention also relates to a circuit arrangement for carrying out the method.

REFERENCES:
patent: 6466507 (2002-10-01), Ryan
patent: 6504790 (2003-01-01), Wolford
patent: 6987700 (2006-01-01), Hong et al.
patent: 7117292 (2006-10-01), Kelly
patent: 2003/0151971 (2003-08-01), Acharya et al.

Affiliated with

Also associated with

Rating

Method and circuit arrangement for controlling write access... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and circuit arrangement for controlling write access..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and circuit arrangement for controlling write access... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3738108