Method and circuit arrangement for clock recovery

Details Method and circuit arrangement for clock recovery Method and circuit arrangement for clock recovery

2005-02-22

2005-02-22

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C327S031000, C327S033000, C327S035000, C327S141000

Reexamination Certificate

active

06859912

ABSTRACT:
Clock recovery from transmitted data signals is carried out entirely digitally, and in a manner that is essentially insensitive to dynamic changes in the phase of the data signal. To this end, at least four phase-shifted sample signals are produced from a predetermined time signal. At least two of these phase-shifted sample signals are selected as a function of the respective phase angles with respect to the data signal, and in each case are supplied separately to a device for time sampling of the data signal with the selected sample signal. One of the devices in each case is connected to an output device for the data signal as a function of the respective phase separations between the data signal and the selected phase-shifted sample signals.

REFERENCES:
patent: 6078200 (2000-06-01), Miyano
patent: 6266799 (2001-07-01), Lee et al.
patent: 6650146 (2003-11-01), Liu et al.
patent: 6657466 (2003-12-01), Sudjian
patent: 20030142770 (2003-07-01), Engl et al.
patent: 0 822 683 (2000-11-01), None

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