Method and circuit architecture for testing a non-volatile memor

Details Method and circuit architecture for testing a non-volatile memor Method and circuit architecture for testing a non-volatile memor

1997-05-30

2000-06-27

Canney, Vincent P.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

G06F 1100

Patent

active

060819111

ABSTRACT:
The invention relates to a circuit architecture for easily carrying out tests on a non-volatile memory device having at least one matrix (2) of memory cells. The architecture is distinctive in that it comprises a bi-directional internal data bus (3) extending from one end to the other of the memory device, a plurality of signal sources (8) inside said memory device, at least one local bus (6) connected to the data bus (3), and timing means (10) for timing the access of the local bus (6) to the data bus (3) and the selective access of the signal sources (8) to the local bus (6) during the same test cycle.

REFERENCES:
patent: 5848077 (1998-12-01), Kamae et al.

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