Method and circuit architecture for testing a non-volatile memor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

G06F 1100

Patent

active

060819111

ABSTRACT:
The invention relates to a circuit architecture for easily carrying out tests on a non-volatile memory device having at least one matrix (2) of memory cells. The architecture is distinctive in that it comprises a bi-directional internal data bus (3) extending from one end to the other of the memory device, a plurality of signal sources (8) inside said memory device, at least one local bus (6) connected to the data bus (3), and timing means (10) for timing the access of the local bus (6) to the data bus (3) and the selective access of the signal sources (8) to the local bus (6) during the same test cycle.

REFERENCES:
patent: 5848077 (1998-12-01), Kamae et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and circuit architecture for testing a non-volatile memor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and circuit architecture for testing a non-volatile memor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and circuit architecture for testing a non-volatile memor will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1793639

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.