Method and cache control circuit for replacing cache lines...

Details Method and cache control circuit for replacing cache lines... Method and cache control circuit for replacing cache lines...

2011-03-29

2011-03-29

Shah, Sanjiv (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S134000

Reexamination Certificate

active

07917700

ABSTRACT:
A method and a cache control circuit for replacing a cache line using an alternate pseudo least-recently-used (PLRU) algorithm with a victim cache coherency state, and a design structure on which the subject cache control circuit resides are provided. When a requirement for replacement in a congruence class is identified, a first PLRU cache line for replacement and an alternate PLRU cache line for replacement in the congruence class are calculated. When the first PLRU cache line for replacement is in the victim cache coherency state, the alternate PLRU cache line is picked for use.

REFERENCES:
patent: 5594886 (1997-01-01), Smith et al.
patent: 6185658 (2001-02-01), Arimilli et al.
patent: 6279086 (2001-08-01), Arimilli et al.
patent: 6282617 (2001-08-01), Tirumala et al.
patent: 6601144 (2003-07-01), Arimilli et al.
patent: 6629210 (2003-09-01), Arimilli et al.
patent: 6662173 (2003-12-01), Hammarlund et al.
patent: 6857048 (2005-02-01), Rankin et al.
patent: 6993628 (2006-01-01), Starke

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