Method and bus prefetching mechanism for implementing...

Details Method and bus prefetching mechanism for implementing... Method and bus prefetching mechanism for implementing...

2007-11-26

2009-02-10

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S100000, C711S154000, C710S056000

Reexamination Certificate

active

07490201

ABSTRACT:
A method, and bus prefetching mechanism are provided for implementing enhanced buffer control. A computer system includes a plurality of masters and at least one slave exchanging data over a system bus and the slave prefetches read data under control of a master. The master generates a continue bus signal that indicates a new or a continued request. The master generates a prefetch bus signal that indicates an amount to prefetch including no prefetching. The master includes a mechanism for continuing a sequence of reads allowing prefetching until a request is made indicating a prefetch amount of zero.

REFERENCES:
patent: 4189768 (1980-02-01), Liptay et al.
patent: 5537574 (1996-07-01), Elko et al.
patent: 6047363 (2000-04-01), Lewchuk
patent: 6067613 (2000-05-01), Balmer
patent: 6075929 (2000-06-01), MacLaren
patent: 6195735 (2001-02-01), Krueger et al.
patent: 6393527 (2002-05-01), Rao et al.
patent: 6636927 (2003-10-01), Peters et al.
patent: 6871246 (2005-03-01), Moyer
patent: 7139878 (2006-11-01), Malik et al.

Affiliated with

Also associated with

Rating

Method and bus prefetching mechanism for implementing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and bus prefetching mechanism for implementing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and bus prefetching mechanism for implementing... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4076308