Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-02-29
2003-09-09
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C370S252000, C370S333000
Reexamination Certificate
active
06618832
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and to a bus interface employing a memory in an integrated circuit which is used to link a bus with an application device to be controlled by the bus.
BACKGROUND OF THE INVENTION
The IEEE1394 bus is a low cost, high performance serial bus. It has a read/write memory architecture and a highly sophisticated communication protocol. Data rates of 100, 200 or 400 Mbit/s can be transmitted in nearly real time. Simultaneously, data can be transmitted bi-directionally. The first ten bits of transmitted address values refer to one of up to 1023 possible IEEE1394 bus clusters. The following six bits of the transmitted address values refer within a specific cluster to one of up to 63 nodes to which an application or device is assigned. Data between nodes can be exchanged without interaction of a host controller. Devices can be connected to or disrupted from the network at any time, allowing a plug and play behaviour.
The standardised cable connection for the nodes has a length of 4.5 m and contains three twisted cable pairs of which two pairs serve for data and control information transmission and the further pair carries supply voltages of 8V to 40V. Three level coding is used: HIGH (H), LOW (L), and HIGH IMPEDANCE (Z). H overrides L, L overrides Z. The characteristic impedance is 110 &OHgr;. There is also a version IEEE1394-1995 of the bus specification including only two twisted pairs of cables on which no power supply voltage is present. The communication protocol has three layers: physical layer, link layer, and transaction layer. Typically, the transaction layer is realised by firmware whereas the other layers are implemented using chip sets.
The physical layer contains analog transceivers and a digital state machine. It handles bus auto-configuration and hot plug. It reclocks, regenerates and repeats all packets and forwards all packets to the local link layer. It carries out-packet framing, for example speed code, prefix, and packet end assembling. It arbitrates and transmits packets from the local link layer. Available IC types are e.g. TSB11C01, TSB11LV01, TSB21LV03, and TSB41LV03 of Texas Instruments, MB86611 of Fujitsu, and 21S750 of IBM.
The link layer performs all digital logic. It recognises packets addressed to the node by address recognition and decodes the packet headers. It delivers packets to higher layers and generates packets from higher layers. It works either isochronous for AV data use or asynchronous for control data use.
In the isochronous mode a channel having a guaranteed bandwidth is established. There is a defined latency. The transmission is performed in 125 &mgr;s time slots or cycles. Headers and data blocks of a packet have separate CRCs (cyclic redundancy check). This mode has a higher priority than the asynchronous data transfer mode.
The asynchronous mode is not time critical, but safe. It operates as an acknowledged service with a busy and retry protocol. Fixed addresses are used. Transmission takes place when the bus is idle. The asynchronous mode handles read request/response, write request/response, and lock request/response. It performs cycle control, CRC generation and validation. Available link layer IC types are e.g. TSB12C01A, TSB12LV21, TSB12LV31, and TSB12LV41 of Texas Instruments, and PDI1394L11 of Philips.
The transaction layer implements asynchronous bus transactions:
Read request/read response
Write request/write response
Lock request/lock response.
As mentioned above it can be implemented by software running on a microcontroller, such as e.g. the i
960
of SparcLite. There may also be an AV (audio video) layer carrying out device control, connection management, timestamping, and packetising.
In IEEE1394 systems, the link layer acts as an interface between an external application and the IEEE1394 bus (through the physical layer).
The external application can be for example a consumer device, such as a set-top-box or a VCR or a DVD player, which delivers/receives latency critical isochronous data and non-latency critical asynchronous data.
The asynchronous data packets are used for the controlling operations or register read/write/lock operations. Isochronous data packets contain information items like video-/audio data.
SUMMARY OF THE INVENTION
For timing decoupling of IEEE1394 bus and application an on-chip memory is used. Because of strongly limited link layer IC on-chip memory capacity it is important to save space when processing with this memory. In case of an ASIC solution for the link layer IC a FIFO (first-in first-out memory) can be used to connect the IEEE1394 bus with the application device and to organise the handling of the asynchronous and isochronous data packets.
It is possible to separate the memory capacity into fixed areas for asynchronous and isochronous data. However, it is advantageous to split the memory capacity in a flexible way in order to be able to meet the requirements for any specific service. Then the memory capacity remaining for other services is to be managed efficiently in order to meet the speed and address requirements. One problem is the efficient management of latency critical isochronous data and non-latency critical asynchronous data within the on-chip memory.
According to the invention, the on-chip memory is prevented on the fly from storing packets containing transmission errors. This feature is true for all asynchronous data packets and in special cases also for isochronous data packets.
In particular, the FIFO memory of the link layer chip is separated into three areas: asynchronous reception area, asynchronous transmission area and isochronous data packet area.
In the asynchronous mode the reception and transmission of IEEE1394 bus data packets is performed in an independent way, whereas in the isochronous mode the reception and transmission of a data packet is carried out in a sequential way, thereby accessing the same memory area.
In receiving mode the data packets coming from the IEEE1394 bus are written word by word into the corresponding memory area. According to the IEEE1394 bus specification the first part of a data packet is defined as the packet-header which is followed by the packet (user) data in the second part.
There are two CRC checkwords (cyclic redundancy check) in an asynchronous IEEE1394 data packet. The first one is appended to the packet header and the second one is appended to the packet or payload data. Due to this specific location of the CRC checkwords within the received packet datastream it is not possible to process the CRC checkwords before writing a data packet into memory. There are at least three ways to process an asynchronous data packet:
a) write all data packet completely into the memory without CRC check. Upon reading the data packets from the memory, the application device will carry out the header CRC check and the packet data CRC check on all data packets and skip the erroneous data packets;
b) in each case, write a complete data packet into the memory thereby carrying out immediate CRC check on this data packet and mark it as ‘erroneous’ if true for the header CRC check and/or the packet data CRC check. Upon reading the data packets from the memory, the application device will check the marking of all data packets and skip the erroneous data packets;
c) in each case, carry out ‘on-the-fly’ a header CRC check or a header CRC check and a packet data CRC check on the incoming data packet using a dedicated CRC check unit and its register(s), and do not write the incoming data packet or its packet data into the memory if the header and/or the packet data is erroneous. Then, initialised by the first header data byte, overwrite the erroneous data packet or packet data, respectively, with the next incoming data packet or packet data.
Advantageously, alternative c) is performed because it saves as much memory space as possible.
Isochronous data packets have a similar structure. The packet header is followed by a header CRC checkword which itself is followed by a payload data field to which a dat
Brune Thomas
Schweidler Siegfried
Dildine R. Stephen
Kiel Paul P.
Thomson Licensing S.A.
Tripoli Joseph S.
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