Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1995-09-27
2002-04-09
Malzahn, David H. (Department: 2787)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S603000
Reexamination Certificate
active
06370556
ABSTRACT:
The invention relates to a method and an arrangement in a transposed digital FIR filter for multiplying a binary input signal by tap coefficients and to a method for designing such a filter.
A digital filter is a software or a specially designed electronic circuit processing discrete signal samples to perform a desired transfer function operation on said signal. The Z transfer function of a digital, i.e. discrete time FIR (Finite Impulse Response) filter has the generic form
H
(
z
)
=
Y
(
z
)
X
(
z
)
=
∑
i
=
0
N
a
i
×
z
-
i
(
1
)
where H(z) is the transfer function of the filter, Y(z) and X(z) represent the output and input of the filter respectively, a
i
represent constant coefficients, i.e. tap coefficients, and z
−i
represents a delay of i clock cycles. The properties of a FIR filter are solely dependent on the tap coefficients a
1
, and thus synthesizing a discrete time filter calls for determining these coefficients so as to provide a filter having the desired characteristics. There are several methods for determining the coefficients. The non-recursive discrete time filter in accordance with equation (1) is normally represented as a block diagram as shown in
FIGS. 1 and 2
.
FIG. 1
illustrates a so-called direct-type FIR (Finite Impulse Response) filter and
FIG. 2
a transposed FIR filter. The filtering function in accordance with equation (1) can be realized by both discrete time filters, but the present invention relates to a transposed FIR filter according to FIG.
2
. As is apparent from
FIGS. 1 and 2
, the discrete time filter is illustrated as a block diagram wherein square blocks
1
perform delaying of the information by one clock cycle z
−1
, triangular blocks
2
represent multiplying operations and circles
3
represent adders.
As stated previously, the characteristics of the filter are dependent on the values of the tap coefficients a
i
. In certain prior art transposed FIR filters, a discrete multiplier unit for each tap coefficient is employed. The drawback of this arrangement is the large number of multiplier units required, which occupy a considerable area on a chip when realized as an integrated circuit and are therefore costly. One known implementation is such wherein the tap coefficients are simple sums of powers of two, i.e. the coefficients are limited to the form
2
−a
+
2
−b
+
2
−c
. Such a solution is attended by the drawback of limitations in the possible coefficients to be realized. These limitations can substantially complicate the realization of the desired signal processing function H(z).
Still another known solution entails the use of a fast multiplier and memory for realizing the filter. Such a solution is illustrated in
FIG. 3
, wherein the necessary delays z
−1
are generated by buffering the values of the input signal X(z) into a RAM memory
41
prior to their application to a multiplier
42
, where they are multiplied by existing coefficients a
i
obtained from a ROM memory. Thereafter the multiplication results are applied to an adder
44
wherein they are summed together with the filter output Y(z). The drawback of such a solution is the chip area occupied by the fast multiplier unit
42
. Further drawbacks include the power consumption of the multiplier unit
42
and, in certain applications, the electromagnetic interference produced thereby in other circuit structures. Furthermore, on account of the limited speed of the multiplier unit, only a limited number of coefficients a
i
can be realized with one multiplier unit. Complex structures require several multiplier units and complex control logic.
The object of the present invention is a transposed digital FIR filter that can be realized as an integrated circuit with several coefficients so as to occupy a substantially smaller chip area in integrated circuit configuration than that occupied in the prior art techniques.
Another object of the present invention is a filter structure suitable for comparatively high clock frequencies, since the speed of the filter structure is not dependent on the requisite number of coefficients.
A further object of the present invention is a digital filter enabling realization of arbitrary coefficients automatically.
These and other objects and advantages of the invention are achieved with a method in a transposed digital FIR filter for multiplying a binary input signal by tap coefficients, which method is characterized in accordance with the invention in that multiplications are performed by using a network of subtractor and/or adder elements wherein at least one element participates in multiplying by at least two different tap coefficients.
Another aspect of the invention is an arrangement in a transposed digital FIR filter for multiplying a binary input signal by tap coefficients. The arrangement is characterized in accordance with the invention in that it comprises a shift register shifting in the direction of the least significant bit and copying the most significant bit or filling in zero values. The register receives the binary input signal of the filter and has outputs for outputting the content of the desired bit positions, a plurality of bit-serial subtractor and adder elements for multiplying the binary input signal by N+1 different tap coefficients by combining output bits of the shift register. The subtractor and/or adder elements are configured as a network wherein at least one subtractor and/or adder element participates in the multiplying operation of at least two different tap coefficients.
One aspect of the invention is a method for designing a transposed digital filter. This method is characterized in accordance with the invention by determining the tap coefficients required in the filter and designing for the filter a network of subtractor and/or adder elements performing the multiplication by tap coefficients, wherein the number of elements is minimized taking into account certain performance criteria for the filter, so that a maximum number of elements participate in the multiplying operation of more than one different tap coefficients.
In the present invention, the tap coefficients are realized by combining numbers divided by powers of two with bit-serial adder and/or subtractor elements, so that at least some of the adder and/or subtractor elements are used for realizing more than one coefficient. In accordance with the invention, all necessary values multiplied by numbers of the form
2
−n
are obtained simultaneously from one shift register. In other words, the “partial sum” or “partial difference” produced by a specific element can be used on the next level of the network of adder and/or subtractor elements simultaneously to form several coefficients. Further, in the arrangement according to the invention the combined use of adder and subtractor elements in producing the coefficients enables the number of elements (+/− operators) to be minimized. It is further possible to minimize the rounding error related to the coefficients by “balancing” the operators against each other.
By means of the invention, the network of bit-serial adder and subtractor elements can be optimized by finding the sum and/or difference of powers of two for the coefficients required, so as to considerably diminish the requisite number of calculation elements in comparison with the prior art solutions. For instance, if a coefficient accuracy of 20 bits is required, ten adder stages on an average are needed for each coefficient in the prior art implementation. With a design according to the invention, it is possible to realize the coefficients with three adder and/or subtractor stages for each coefficient. At the same time, the number of series-connected elements required is characteristically diminished. With the construction of the invention, arbitrary coefficients can be realized. A still another advantage of the invention is a low number of logic levels, and thus the maximum operating frequency is very high. When the invention is realized as an i
Eerola Ville
Husu Timo
Ingalsuo Seppo
Pajarre Eero
Ritoniemi Tapani
Ackerman Stephen B.
Knowles Billy
Malzahn David H.
Saile George O.
Tritech Microelectronics, Ltd
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