Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-12-11
2003-12-16
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06665855
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed generally to semiconductors and their design and development involving hardware simulation (or emulation). More particularly, the invention relates to hardware emulation methods and arrangements involving reconfigurable and reusable circuits in an IC reference platform for expediting the design time of customized chips.
BACKGROUND OF THE INVENTION
The electronics industry continues to strive for high-powered, high-functioning circuits. Significant achievements in this regard have been realized through the fabrication of very large-scale integration of circuits on small areas of silicon wafer. Integrated circuits of this type are developed through a series of steps carried out in a particular order. The main objective in designing such devices is to obtain a device that conforms to geographical features of a particular design for the device. To obtain this objective, steps in the designing process are closely controlled to insure that rigid requirements are realized.
Semiconductor devices are used in large numbers to construct most modem electronic devices. In order to increase the capability of such electronic devices, it is necessary to integrate even larger numbers of such devices into a single silicon wafer. As the semiconductor devices are scaled down (i.e., made smaller) to form a larger number of devices on a given surface area, the structure of the devices and the fabrication techniques used to make such devices have become more refined. This increased ability to refine such semiconductor devices has lead to an ever-increasing proliferation of customized chips, and with each chip serving a unique function and application. This, in turn, has lead to various techniques to design and successfully test chips efficiently and inexpensively.
For many chip designs, customized chips are made by describing their functionality using a hardware-description language (HDL), such as Verilog or VHDL. The hardware description is often written to characterize the design in terms of a set of functional macros. The design is computer simulated to ensure that the custom design criteria are satisfied. For highly-complex custom chip designs, the above process can be burdensome and costly. The highly integrated structure of such chips leads to unexpected problems, such as signal timing, noise-coupling and signal-level issues. Consequently, such complex custom chip designs involve extensive validation. This validation is generally performed at different stages using a Verilog or VHDL simulator. Once validated at this level, the Verilog or VHDL HDL code is synthesized, for example, using “Synopsys,” to a netlist that is supplied to an ASIC (Application Specific Integrated Circuit) foundry for prototype fabrication. The ASIC prototype is then tested in silicon. Even after such validation with the Verilog or VHDL simulator, unexpected problems are typical. Overcoming these problems involves more iterations of the above process, with testing and validation at both the simulation and prototype stages. Such repetition significantly increases the design time and cost to such a degree that this practice is often intolerable in today's time-sensitive market.
Accordingly, there is a need for a way to develop customized chips that overcomes the above-mentioned deficiencies. The present invention addresses this need, and other needs, by way of a rapid silicon prototyping (RSP) process and arrangement in which a typical development period (from initial design to new product) can be reduced by more than fifty percent.
SUMMARY OF THE INVENTION
The present invention relates to a semiconductor device designed using a rapid silicon process and/or processing arrangement. According to the present invention, the design effort of such devices is significantly benefited in connection with the design validation phase of the overall device implementation.
According to one embodiment, a rapid silicon process and processing arrangement involves the design of a high-complexity custom chip using design re-use, and on-chip bus architectures in a way that improves the ability of designers to create advanced custom integrated circuits (ICs) faster and with higher probabilities of success.
Consistent with one embodiment, the present invention is directed to a method for designing a semiconductor circuit arrangement, including its validation. The method comprises: providing a deconfigurable and extendible reference-chip development platform that is programmable, and that includes a programmable circuit and a plurality of functional block macros; using a collection of functional block macros at least one of which is obtained from the deconfigurable and extendible reference-chip development platform; extending the deconfigurable and extendible reference-chip development platform, including communicatively coupling at least one external device with the reference-chip development platform, and thereby providing an extended reference-chip development platform that enables co-development and co-validation of hardware and software. A subset of the collection of functional block macros can then be processed, e.g. synthesized, to the programmable circuit, and then a hardware representation of the synthesized subset of functional block macros in the programmable circuit can be validated within the extended reference-chip development platform.
Consistent with another embodiment, the present invention is directed to a rapid silicon process involving the validation of a FPGA and its implementation to a finished ASIC. This method embodiment of the present invention comprises the above-characterized method and in addition using at least one of the functional block macros in the subset from a functional block macro obtained from the deconfigurable and extendible reference-chip development platform and reusing this same functional block macro(s) in the subset by retargeting to an ASIC that is developed from the hardware representation.
According to another embodiment, the present invention is directed to a system for designing a semiconductor circuit arrangement. The system comprises: a deconfigurable and extendible reference-chip development platform that is programmable, and includes a hardware reconfigurable circuit and a plurality of functional block macros; a collection of functional block macros at least one of which is obtained from the deconfigurable and extendible reference-chip development platform; an interface circuit configured and arranged to extend the deconfigurable and extendible reference-chip development platform, including a two-way buffer arrangement and logic circuitry adapted to communicatively couple a plurality of external devices with the reference-chip development platform, and thereby provide an extended reference-chip development platform that enables co-development and co-validation of hardware and software; a synthesizer adapted to cause the subset of the collection of functional block macros to be represented as a configuration of the hardware reconfigurable circuit; and wherein the extended reference-chip development platform is adapted to validate the configuration in the hardware reconfigurable circuit within the extended reference-chip development platform.
Another aspect of the present invention is directed to a system for designing a semiconductor circuit arrangement. The system comprises: a deconfigurable and extendible reference-chip development platform that is programmable, and includes a programmable circuit and a plurality of functional block macros; a collection of functional block macros at least one of which is obtained from the deconfigurable and extendible reference-chip development platform; an interface circuit configured and arranged to extend the deconfigurable and extendible reference-chip development platform, including a bus and logic circuitry adapted to communicatively couple at least one external device with the reference-chip development platform, and thereby provide an extended reference-chip development platform that enab
Bapst Mark
Payne Robert
Pontius Timothy
Koninklijke Philips Electronics , N.V.
Siek Vuthe
Zawilski Peter
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