Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-10-05
2004-07-27
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06769105
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor design and manufacture. In particular the present invention discloses gridless semiconductor architectures and methods for designing and manufacturing gridless semiconductor integrated circuits.
BACKGROUND OF THE INVENTION
An integrated circuit (“IC”) is a semiconductor device that includes many electronic components (e.g., transistors, diodes, inverters, etc.). These electrical components are interconnected to form larger scale circuit components (e.g., gates, cells, memory units, arithmetic units, controllers, decoders, etc.) on the IC. The electronic and circuit components of IC's are jointly referred to below as “components.”
An IC also includes multiple layers of metal and/or polysilicon wiring that interconnect its electronic and circuit components. For instance, many IC's are currently fabricated with five metal layers. In theory, the wiring on the metal layers can be all-angle wiring (i.e., the wiring can be in any arbitrary direction). Such all-angle wiring is commonly referred to as Euclidean wiring. In practice, however, each metal layer typically has a preferred wiring direction in an attempt to maximize the number of signal wires placed on each wiring layer by preventing intersections. In current ICs, the preferred direction alternates between successive metal layers. Most IC's use the “Manhattan” wiring model, which specifies alternating layers of preferred-direction horizontal and vertical wiring. (Viewed from above, the horizontal and vertical wiring resemble the orthogonal streets of Manhattan.) In the Manhattan wiring model, essentially all of the interconnect wires are horizontal or vertical.
Design engineers design IC's by transforming circuit description of the IC's into geometric descriptions, called layouts. To create an integrated circuit layout, design engineers typically use electronic design automation (“EDA”) applications. These EDA applications provide sets of computer-based tools for creating, editing, and analyzing IC design layouts. EDA applications create layouts by using geometric shapes that represent different materials and devices on IC's. For instance, EDA tools commonly use rectangular lines to represent the wire segments that interconnect the IC components. These EDA tools also represent electronic and circuit IC components as geometric objects with varying shapes and sizes. For the sake of simplifying the discussion, these geometric objects are shown as rectangular blocks in this document. Also, in this document, the geometric representation of an electronic or circuit IC component by an EDA application is referred to as a “circuit module.”
EDA applications typically illustrate circuit modules with electrical interface “pins” on the sides of the circuit modules. These pins connect to the interconnect lines, the “wiring” used to connect the various circuit modules. A collection of pins that are, or need to be, electrically connected is referred to as a net.
FIG. 1
illustrates a simple example of an IC layout
100
. The IC layout
100
includes five circuit modules
105
,
110
,
115
,
120
, and
125
with pins
130
-
160
. Four interconnect lines
165
-
180
connect these modules through their pins. In addition, five nets specify the interconnection between the pins. Specifically, pins
35
,
45
, and
60
define a three-pin net, while pins
30
and
55
, and pins
40
and
50
respectively define two two-pin nets. As shown in
FIG. 1
, a circuit module (such as
105
) can have multiple pins on multiple nets.
The IC design process entails various operations.
FIG. 2
illustrates the overall process for laying out an integrated circuit device once the logical circuit design of the integrated circuit device has been completed. Some of the physical-design operations that EDA applications commonly help perform to layout an integrated circuit include: (1) floor planning (in step
210
of FIG.
2
), which divides the integrated circuit layout area into different sections devoted to different purposes (such as ALU, memory, decoding, etc.); (2) placement (in step
220
of FIG.
2
), which finds the alignment and relative orientation of the circuit modules; (3) global and detailed routing (in steps
230
and
240
of FIG.
2
), which completes the interconnects between the circuit modules as specified by the net list; (4) compaction (in step
250
of FIG.
2
), which compresses the layout in all directions to decrease the total IC area; and (5) verification (in step
250
of FIG.
2
), which checks the layout to ensure that it meets design and functional requirements.
Referring to step
210
of
FIG. 2
, layout designers initially perform high-level floor planning. During the high-level floor planning, layout designers decide roughly where various large circuit blocks will be placed on the integrated circuit. The layout designers then perform a “placement” step
220
. During the placement step, the layout designers place all the circuit cells into specific locations while following the high-level floor planning map of step
210
. The placement step
220
is largely performed with the help of EDA tools that help select optimized placement.
FIG. 3
a
illustrates an example of two large circuit modules
310
and
320
and two smaller circuit modules
330
and
340
placed onto an integrated circuit layout. The various circuit modules may be rotated ninety degrees as necessary to obtain a desired layout.
Operation (
3
), routing, is generally divided into two sub steps: global routing (step
230
of
FIG. 2
) and detailed routing (step
240
of FIG.
2
). Global routing divides an integrated circuit into individual global routing areas. Then, a global routing path is created for each net by listing the global routing areas that the net must pass through. After global routes have been created, each individual global routing area is then processed with detailed routing. Detailed routing creates specific individual routing paths for each net within that global routing area.
Global routing is a step that is used to divide an extremely difficult overall routing problem into smaller routing problems in a “divide and conquer” approach. The overall task of routing an integrated circuit is to route together all electrically common signals on the integrated circuit. The global routing step divides an integrated circuit area into individual global routing areas and then determines the specific global routing areas that each electrically common signal must pass through. The list of circuit modules and pins that need to be connected for a specific electrically common signal is known as a net. The contiguous path through the global routing areas is known as a “global routing path” for that net. An example of global routing is provided with reference to
FIGS. 3
a
and
3
b.
Referring to
FIG. 3
a
, there are three different electrically common signals A, B, and C. The electrical signal terminations for electrically common signals A, B, and C illustrated on
FIG. 3
a
as marked dots. The electrical signal terminations are commonly referred to as “pins”. Furthermore, the integrated circuit of
FIG. 3
a
has been divided into sixteen different global routing areas that are labeled 01 to 16. For each electrically common signal, a net is created containing a list of all the global routing areas that have common electrical signal termination pins. Thus, for example, the net of electrical signal A is 01, 02, 08, and 12 since electrical signal A has termination pins in those labeled global routing areas.
After creating the various nets, global routing path lists are then constructed from the various nets.
FIG. 3
b
illustrates the integrated circuit of
FIG. 3
a
with the addition of global routing path lists and roughly sketched global routing paths. (The actual specific routing path is not determined during the global routing step, just the list of global routing areas that a signal must enter or pass through.) The global routing paths join together glo
Caldwell Andrew
Teig Steven
Cadence Design Systems Inc.
Rossoshek Yelena
Siek Vuthe
Stattler Johansen & Adeli LLP
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