Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
1998-11-12
2001-09-11
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S058000, C710S060000, C711S153000
Reexamination Certificate
active
06289403
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for controlling a data transmission.
In contemporary data transmission means, particularly in personal computers, what is known as a PCI bus (Peripheral Component Interconnect) is set up for a connection of peripheral means such as an LAN (Local Area Network). The peripheral means are connected to the PCI bus via defined interfaces which are controlled via what are known as I/O controllers. For a data transfer between the peripheral means and other units such as a processor unit or a main memory connected to the processor unit via a processor bus, for example, the PCI bus is connected to the processor bus via a coupling means frequently referred to as a bridge.
The data sheet “82439HX System Controller (TXC)” of the firm Intel (July 1996, order number 290551-001, p. 5 and 6 in particular) teaches such a bridge which connects a PCI bus to a processor bus (processor host bus) and a central memory (main memory). The bridge comprises two temporary storage units for a data transfer between the PCI bus and a processor unit, or respectively, the main memory. Those data which are transmitted from the processor unit to a peripheral means connected to the PCI bus, or vice versa, on the basis of an initiative of the processor unit are temporarily stored in a first temporary storage unit. Those data which are transmitted to the main memory from a peripheral means connected to the PCI bus, or vice versa, on the basis of an initiative of said means are temporarily stored in a second temporary storage unit.
The first and the second temporary storage units are respectively fashioned as FIFO (First In First Out) memories in which the data to be transmitted are stored together with an address identifying the respective peripheral means.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method by which the degree of effectivity of a data transfer between two system busses is increased.
For a better understanding of the functions and the operation of a bridge it seems necessary to initially elaborate on known principles with the aid of a PCI bus architecture realized in a personal computer.
If a processor unit requests data from a peripheral means, then the processor unit outputs a read request to the processor bus along with the address of an I/O controller allocated to the peripheral means. A first module with a first functional unit of the bridge recognizes the address of the peripheral means and transmits the read request to a second module of the first functional unit. This outputs the read request with the address of the I/O controller onto the PCI bus. The addressed I/O controller recognizes the read request directed thereto and outputs the requested data to the PCI bus. The second module of the first functional unit incorporates the requested data into a first submemory of the FIFO memory of the first functional unit. The first module of the first functional unit reads the data from the first submemory of the FIFO memory and outputs them to the processor bus, from which they are read by the processor unit.
When a processor unit transmits data to a peripheral means, the processor unit outputs a write request to the processor bus and subsequently outputs the data to be transmitted to the processor bus along with the address of an I/O controller allocated to the peripheral means. The first module of the first functional unit of the bridge recognizes the address of the peripheral means and transmits the write request to the second module of the first functional unit. The first module simultaneously writes the data to be transmitted into a second submemory of the FIFO memory of the first functional unit. The second module applies the write request to the PCI bus. The addressed I/O controller recognizes the write request directed thereto and signals its readiness to receive data to the bridge. The second module of the first functional unit then reads the data from the second submemory of the FIFO memory and outputs them to the PCI bus, the I/O controller taking them over from there.
If data of a peripheral means are to be stored in the main memory on the basis of a request of an I/O controller, the I/O controller writes these data to the PCI bus along with the address at which the data should be stored in the main memory. A first module of a second functional unit recognizes the address in the main memory and writes the data with the appertaining address into a first submemory of a FIFO memory of the second functional unit. A second module of the second functional unit reads the data from the first submemory of the FIFO memory and outputs them to the processor bus together with the address at which the data are to be stored in the main memory. The main memory recognizes the addresses and stores the data at the corresponding location in the main memory.
If data is to be read from the main memory on the basis of a request of an I/O controller, the I/O controller outputs a corresponding read request to the PCI bus with the address of the desired data in the main memory. The first module of the second functional unit recognizes the address in the main memory and transmits the read request to the second module of the second functional unit. This outputs the read request to the processor bus together with the address in the main memory. The main memory recognizes the read request and outputs the requested data to the processor bus. The second module of the second functional unit takes over the data from the processor bus and writes the requested data into a second submemory of the FIFO memory of the second functional unit. The first module of the second functional unit reads the data from the second submemory of the FIFO memory and outputs them to the PCI bus together with the address of the requested I/O controller, from which they are read by the I/O controller.
A distribution of free bus capacities, that is, the allocation of who can write data to a bus as “master”, ensues via an arbitration module specific to the bus. An arbitration module of the processor bus manages request messages released by the processor unit and by the second module of the second functional unit, for example, for an accessing of the processor bus. An arbitration module of the PCI bus manages request messages released by the I/O controllers and by the second module of the first functional unit, for example, for an accessing of the PCI bus.
Different priorities can be allocated to the individual request messages for a system bus; that is, given time-critical data a timely allocation of the master function for the system bus to the waiting unit ensues even given a high loading of the corresponding system bus. A higher priority is assigned to a request message for speech data to be transmitted than to a request for the transmission of non-time-critical security data, for example.
The data transfer between peripheral means, or respectively, units of the central computer system, and the bridge ensues by means of burst operations. In burst operations a plurality of data packets are transmitted in succession, whereby the appertaining destination address is not co-transmitted for every individual data packet. Only the address of a memory cell into which the first data packet is to be written is transmitted. The subsequent data packets are automatically written into the subsequent memory cells.
The length of a burst operation is individually adjustable for each unit transmitting data. The length is determined by a latency timer specific to the unit. The length of a burst operation is explicitly prescribed by the time set for the latency timer, that is, the time during which a unit may write data onto a system bus. By the prescription of how long a unit may occupy a system bus it is guaranteed that each unit connected to the system bus can transmit the requested data even given high loading of the system bus.
The inventive method offers the advantage that in a transmission of data between the system bus and the peripheral bus an interm
Lee Thomas
Perveen Rehana
Schiff & Hardin & Waite
Siemens Aktiengesellschaft
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