Method and arrangement for contact-connecting semiconductor...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip

Reexamination Certificate

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Details

C257S678000, C257S790000, C257SE23169

Reexamination Certificate

active

07915739

ABSTRACT:
The method comprises the following steps: the substrate in the form of a one-piece basic substrate (4) is prepatterned into regions corresponding to future modules, pads of the semiconductor chip (1) are then contact-connected in predetermined regions of a first area of the basic substrate (4) and on the top side (12) of the prepatterned basic substrate (4) and on one area side of the semiconductor chip (1) a first adhesive layer (16) is applied, a second adhesive layer (17) is subsequently applied to the other area side of the semiconductor chip (1), and a curing of the adhesive layers (16, 17) and a final patterning of the metallic basic substrate (4) are then effected.

REFERENCES:
patent: 5336931 (1994-08-01), Juskey et al.
patent: 7179683 (2007-02-01), Low et al.
patent: 2003/0052419 (2003-03-01), Ujiie et al.
patent: 4337921 (1995-05-01), None
patent: 0818236 (1996-07-01), None
patent: 2004135192 (2004-04-01), None
International Search Report prepared by the European Patent Office dated Oct. 23, 2006; International Application No. PCT/IB2006/050524; Applicant, ASSA Abloy Identification Technology Group AB.
Written Opinion of the International Searching Authority prepared by the European Patent Office dated Oct. 23, 2006; International Application No. PCT/IB2006/050524; Applicant, ASSA Abloy Identification Technology Group AB.

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