Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-08-26
2002-04-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S018000
Reexamination Certificate
active
06372627
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to semiconductor device assemblies, and more particularly, to techniques for analyzing and debugging circuitry associated with multi-layer type and flip-chip type bonded integrated circuits.
BACKGROUND OF THE INVENTION
In recent years, the semiconductor industry has seen tremendous advances in technology that has permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for multiple layers of metal interconnects for routing signals to and from so many circuit devices, and increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages, which receive the die, for connecting the packaged device to external systems such as a printed circuit board.
There have been a number of semiconductor dies and packaging types used to address these issues. Semiconductor devices that have multiple layers of metal signal-routing interconnects are often referred to as multi-layer devices. Multi-layer devices typically have two or more layers (or levels) of metal interconnects built up over the portion of the die having the active devices. At this “circuit” or “front” side of the die, where the transistors and other active circuitry are generally formed, is a very thin epitaxially-grown silicon layer on a single crystal silicon wafer from which the die is singulated. The circuit side of the die is positioned very near the package, and opposes the back side of the die. The substrate between the back side and the circuit side of the die is typically a bulk silicon, such as single crystalline silicon.
To increase the number of pad sites available for a die, especially for multilayer type dies, various semiconductor packaging types have been developed. One increasingly popular packaging technique is called “controlled collapse chip connection” or “flip-chip” packaging. In this technology, the bonding pads are provided with metal (solder) bumps. The bonding pads need not be on the periphery of the die and hence are moved to the site nearest the transistors and other circuit devices formed in the die. As a result, the electrical path to the pad is shorter. Electrical connection to the package is made when the die is flipped over the package with corresponding bonding pads and soldered. Once a flip-chip die is attached to the package, the back side portion of the die remains exposed. As a result, the dies are often referred to as “flip-chip” devices. Each bump connects to a corresponding package inner lead. The packages that result are lower profile, have lower electrical resistance, and a shortened electrical path.
The output terminals of such packages vary depending on the package type. For example, some output terminals are ball-shaped conductive bump contacts (usually solder, or other similar conductive material), and they are typically disposed in a rectangular array. These packages are occasionally referred to as “Ball Grid Array” (BGA). Another type of package, commonly known as a “Pin Grid Array” (PGA) package, implements the output terminals as pins.
The positioning of the circuit side of a die can be an important factor in the testing and analysis of the integrated circuit because oftentimes such testing and analysis involves device modification or re-routing of signals connected through the interconnects. For a multi-layer device, performing device modification or re-routing is not a simple task compared with, for example, a device having only one layer metal process. Many desired nodes are buried under other upper level metals, making it very difficult to access and even harder to connect from these nodes to other locations.
For a flip-chip device, which often includes multi-layer metals, performing device modification or re-routing is even more difficult. For example, one particular type of flip-chip package, known as the C4 type, increases the possible I/O numbers. For this kind of flip-chip with multi-layer metals, accessing the circuitry via the exposed back side of the die becomes necessary for probing and circuit repair because the circuit side of the flip-chip die is not visible or accessible for viewing using optical or scanning electron microscopy. Using the exposed back side of the die is challenging since the transistors are in a very thin layer (e.g., about 10 micrometers) of silicon buried under the bulk silicon (e.g., greater than 500 micrometers).
Although the circuit of the integrated circuit (IC) is buried under the bulk silicon (i.e., the single crystalline silicon), infrared (IR) microscopy is capable of imaging the circuit because silicon is relatively transparent in these wavelengths of the radiation. However, because of the adsorption losses of IR radiation in silicon, it is generally required to thin the die to less than about 100 microns in order to view the circuit using IR microscopy. To illustrate this difficulty, on a die that is 725 microns thick, at least 625 microns of silicon must be removed (or thinned) before IR microscopy can be used.
Thinning a flip-chip bonded die for failure analysis can be time consuming and burdensome. According to one common approach, thinning is accomplished in two or three steps. First, the die is thinned across the whole die surface and is referred to as “global thinning.” Global thinning is done to allow viewing of the active circuit from the back side of the die using IR microscopy. Mechanical polishing is one method for global thinning. Once an area is identified as an area of interest and it is determined that access is needed to a particular area of the circuit, local thinning techniques can be used to thin an area smaller than the die size.
Focused ion-beam (FIB) milling is commonly used for thinning the back side of dice to permit e-beam signal acquisition to determine voltage levels of the nodes (e.g., to the millivolt level) while the part is actually operating. FIB milling is effective because it permits for local thinning to expose and/or access target circuitry nondestructively. For flip-chip multi-layer metal devices with advanced processes to expose the lower level metal nodes, the local thinning is implemented by milling deep, narrow holes through the back side of the die. For effective e-beam signal acquisition, the depth of the FIB hole should increase with its width. The ideal aspect ratio (depth to width) of a FIB hole is one to one. For a typical flip-chip having a relatively thick bulk silicon region between the back side and the circuit side of the die, the thickness of FIB holes must have an aspect ratio of about five to one. With this degree of aspect ratio, e-beam signal acquisition is very difficult.
This problem has been addressed by bringing up the lower level metal nodes via FIB milling and FIB deposition. For example, one such approach involves FIB milling to expose the desired lower metal nodes (and sometimes other metal nodes in the process), and FIB depositing insulator material to isolate the exposed nodes so that they do not short during subsequent metal deposition. Next, the FIB is used to re-mill through the deposited insulator material to expose just the desired lower metal nodes. This re-milling step is very difficult due to the poor contrast between underlying metal and the deposited insulator material. Finally, metal (Pt or W) is FIB deposited to back-fill the holes opened by the above re-milling step. This is a burdensome, time-consuming process that enjoys a very low success rate.
Accordingly, there is a need for improved systems and methods to test and analyze such integrated circuits.
SUMMARY OF THE INVENTION
Accord
Gilfeather Glen
Li Susan
Ring Rosalinda M.
Advanced Micro Devices , Inc.
Le Dung A
Nelms David
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