Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-06-26
2011-12-13
Alsip, Michael (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C711S128000, C711S129000, C711S133000, C711SE12038, C712S003000, C712S016000, C712S203000
Reexamination Certificate
active
08078804
ABSTRACT:
A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.
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Guidetti Elio
Notarangelo Giuseppe
Pappalardo Francesco
Salurso Elena
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Alsip Michael
Jorgenson Lisa K.
STMicroelectronics N.V.
STMicroelectronics S.r.l.
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