Method and architecture for reducing the power consumption...

Details Method and architecture for reducing the power consumption... Method and architecture for reducing the power consumption...

2006-06-06

2006-06-06

Mai, Son (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S227000

Reexamination Certificate

active

07057960

ABSTRACT:
A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) controlling the background operations in one or more sections of the memory array in response to one or more control signals and (ii) presenting the one or more control signals and one or more decoded address signals to one or more periphery array circuits of the one or more sections.

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